Method of fabricating a field effect transistor
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsSylvain Barraud, Joris Lacord
Life of this patent
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Abstract
A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.
Claims15
A method for producing an FET transistor, comprising at least the implementation of the following successive steps:
- producing an FET transistor channel comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces substantially perpendicular to a face of the substrate on which the channel is arranged and substantially parallel to a direction of flow of a conduction current intended to pass through the channel when the FET transistor is in an ON state;
- producing at least two dummy gates, each arranged against one of the first and second side faces of the channel;
- etching a first of the two dummy gates, forming at least one first gate location against the first side face of the channel;
- producing at least one first gate in the first gate location and at least against the first side face of the channel;
- etching a second of the two dummy gates, forming at least one second gate location against the second side face of the channel;
- and
- producing at least one second gate in the second gate location and at least against the second side face of the channel.
An FET transistor comprising at least:
- a substrate;
- a channel formed of a stack of at least two nanowires arranged on the substrate, each nanowire comprising first and second opposite side faces substantially perpendicular to a face of the substrate on which the channel is arranged and substantially parallel to a direction of flow of a conduction current intended to pass through the channel when the FET transistor is in an ON state, and each nanowire comprising opposite lower and upper faces substantially parallel to said face of the substrate;
- a first gate arranged against the first side faces of the nanowires and comprising at least one extension region extending between the nanowires in such a way as to form an interdigitated gate and covering the upper face of a first of the nanowires and a lower face of a second of the nanowires;
- and
- a second gate,
- and wherein the second gate covers, among all the faces of the nanowires, only the second side face of at least one of the nanowires.
Dependencies are inferred from the claim text.