Transistors with an asymmetrical source and drain

A method of forming a structure for a field-effect transistor, the method comprising:

• forming a first gate structure that extends over a semiconductor fin;
• forming an epitaxial semiconductor layer of a first source/drain region on a first portion of the semiconductor fin, the epitaxial semiconductor layer include a first concentration of a dopant;
• and
• forming a second source/drain region including a second concentration of the dopant in a second portion of the semiconductor fin,
• wherein the first source/drain region and the second source/drain region have the same conductivity type, the semiconductor fin has a top surface, the second source/drain region is positioned in the second portion of the semiconductor fin entirely below the top surface of the semiconductor fin, the first gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the first gate structure, the second source/drain region positioned adjacent to the second sidewall of the first gate structure, the first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.