Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy

A method of forming a vertical transport field effect transistor, comprising:

• forming a bottom spacer layer on a bottom source/drain layer;
• depositing a gate dielectric layer on the bottom spacer layer and a thinned portion, tapered upper portion, and tapered lower portion of a vertical fin on the bottom source/drain layer, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion;
• and
• depositing a work function metal layer on the gate dielectric layer.

A vertical transport field effect transistor, comprising:

• a vertical fin including a thinner portion, an upper tapered portion, and a lower tapered portion on a bottom source/drain;
• a gate dielectric layer on the vertical fin, wherein the gate dielectric layer has an angled portion on each of the upper tapered portion and lower tapered portion;
• a work function metal layer on the gate dielectric layer, wherein a top edge of the work function metal layer is below the top edge of the gate dielectric layer on the upper tapered portion;
• and
• an encapsulation layer on the work function metal layer.