Fabricating a gate-all-around (GAA) field effect transistor having threshold voltage asymmetry by thinning source side lateral end portion of the nanosheet layer

A method of fabricating a gate-all-around field-effect transistor having threshold voltage asymmetry, comprising:

• obtaining a monolithic semiconductor structure including:
• a vertical stack of nanosheet layers and sacrificial semiconductor layers, the nanosheet layers and the sacrificial semiconductor layers being arranged in alternating sequence, each of the nanosheet layers including a source side lateral end portion, a drain side lateral end portion, and a middle portion between and integral with the source side lateral end portion and the drain side lateral end portion, the source side lateral end portion and the drain side lateral end portion extending laterally beyond the sacrificial semiconductor layers;
• a dummy gate on the vertical stack;
• and
• outer dielectric spacers adjoining the dummy gate;
• thinning the source side lateral end portions of the nanosheet layers;
• forming inner dielectric spacers between the source side lateral end portions and between the drain side lateral end portions of the nanosheet layers, wherein forming the inner dielectric spacers includes:
• forming an oxide layer on the sacrificial semiconductor layers;
• and
• forming a dielectric outer layer on the oxide layer;
• epitaxially growing a source region and a drain region, respectively, on the source side lateral end portions and the drain side lateral end portions of the nanosheet layers,
• removing the dummy gate to form a trench bounded by the dielectric outer spacers;
• removing the sacrificial semiconductor layers selectively with respect to the nanosheet layers to form a plurality of spaces between and in alternating sequence with the nanosheet layers;
• forming a gate dielectric layer within the trench and on the nanosheet layers;
• and
• forming a metal gate over the gate dielectric layer, wherein forming the metal gate further includes forming relatively thick metal gate portions between the source side lateral end portions of the nanosheet layers and relatively thin metal gate portions between the middle portions of the nanosheet layers;
• and
• removing portions of the inner dielectric spacers prior to forming the gate dielectric layer and to forming the metal gate over the gate dielectric layer, wherein removing portions of the inner dielectric spacers further includes removing portions of the oxide layer selective to the dielectric outer layer;
• wherein the nanosheet layers consist essentially of monocrystalline silicon and the sacrificial semiconductor layers consist essentially of silicon germanium.

A method of fabricating a gate-all-around field-effect transistor having threshold voltage asymmetry, comprising:

• obtaining a monolithic semiconductor structure including:
• a vertical stack of nanosheet layers and sacrificial semiconductor layers, the nanosheet layers and the sacrificial semiconductor layers being arranged in alternating sequence, each of the nanosheet layers including a source side lateral end portion, a drain side lateral end portion, and a middle portion between and integral with the source side lateral end portion and the drain side lateral end portion, the source side lateral end portion and the drain side lateral end portion extending laterally beyond the sacrificial semiconductor layers;
• a dummy gate on the vertical stack;
• and
• outer dielectric spacers adjoining the dummy gate;
• vertically thinning the source side lateral end portions of the nanosheet layers;
• forming inner dielectric spacers vertically between the source side lateral end portions and vertically between the drain side lateral end portions of the nanosheet layers, wherein forming the inner dielectric spacers includes:
• forming an oxide layer on the sacrificial semiconductor layers;
• and
• forming a dielectric outer layer on the oxide layer;
• epitaxially growing a source region and a drain region, respectively, on the source side lateral end portions and the drain side lateral end portions of the nanosheet layers,
• removing the dummy gate to form a trench bounded by the dielectric outer spacers;
• removing the sacrificial semiconductor layers selectively with respect to the nanosheet layers to form a plurality of spaces between and in alternating sequence with the nanosheet layers;
• forming a gate dielectric layer within the trench and on the nanosheet layers;
• and
• forming a metal gate over the gate dielectric layer, wherein forming the metal gate further includes forming relatively thick metal gate portions between the source side lateral end portions of the nanosheet layers and relatively thin metal gate portions between the middle portions of the nanosheet layers;
• and
• removing portions of the inner dielectric spacers prior to forming the gate dielectric layer and to forming the metal gate over the gate dielectric layer, wherein removing portions of the inner dielectric spacers further includes removing portions of the oxide layer selective to the dielectric outer layer.