Self-aligned and robust IGBT devices
AssigneeIpower Semiconductor
InventorHamza Yilmaz
Life of this patent
Estimating the term…
Abstract
A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.
Claims6
A method of forming a vertical insulated gate bipolar transistor (IGBT) device, comprising:
- providing a semiconductor substrate of n conductivity type having a front side and a backside;
- forming column structures of p conductivity type fully surrounding an active region in the front side of the semiconductor substrate, forming each column structure including:
- forming a column trench in the front side of the semiconductor substrate, the trench including trench side walls and a trench floor,
- forming dielectric spacers on the trench side walls,
- forming a column deep region extending downwardly from the trench floor by applying dopants of p conductivity type into the semiconductor substrate through the trench floor,
- filling the trench with poly silicon of p conductivity type which is in contact with the column deep region;
- and
- depositing an oxide layer including silicon oxide onto the front side of the semiconductor substrate including the column trenches filled with the poly silicon;
- planarizing the oxide layer;
- depositing an etch stop layer including silicon nitride on the oxide layer;
- applying a photomask on the etch stop layer;
- and
- forming a plurality of metal-oxide-semiconductor field-effect transistor (MOSFET) cells in the active region fully surrounded by the column structures,
- wherein the substrate of n conductivity type is common to the plurality of MOSFET cells formed in the active area, and
- wherein the column structures are substantially deeper than the MOSFET cells to protect the cells from high voltage.
Dependencies are inferred from the claim text.