Gate formation with varying work function layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJin-Dah Chen, Stan Chen, Han-Wei Wu
Life of this patent
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Abstract
A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.
Claims20
A semiconductor device comprising:
- a first fin;
- a second fin, wherein a region between the first fin and the second fin is free of another fin, wherein the region extends from the first fin to the second fin;
- a first work function metal layer extending over the first fin, the first work function metal layer terminating at a first location closer to the first fin than the second fin, the first location being between the first fin and the second fin;
- a second work function metal layer extending over the first work function metal layer, the second work function metal layer terminating at a second location closer to the second fin than the first fin, the second location being between the first fin and the second fin;
- and
- a gate electrode over the first fin and the second fin.
A semiconductor device comprising:
- a first dielectric layer over a first fin, a second fin, and an isolation region on opposing sidewalls of the first fin and the second fin;
- and
- a gate structure extending through the first dielectric layer to the first fin and the second fin, wherein the gate structure comprises:
- a gate dielectric layer over the first fin and the second fin;
- a first work function layer over the first fin, the first work function layer terminating at a first position closer to the first fin than the second fin;
- a second work function layer over the first fin and the first work function layer, the second work function layer terminating at a second position closer to the second fin than the first fin;
- a third work function layer over the first fin, the first work function layer, and the second fin;
- and
- a conductive fill over the first fin, the second fin, and the third work function layer.
A semiconductor device comprising:
- a first fin;
- a second fin;
- isolation regions extending around the first fin and the second fin;
- an interlayer dielectric over the first fin, the second fin, and the isolation regions;
- a gate spacer extending through the interlayer dielectric;
- and
- a gate structure extending through the interlayer dielectric, the gate structure having a first end and a second end, the gate structure comprising:
- a gate dielectric layer extending through the interlayer dielectric, wherein the gate spacer is interposed between the gate dielectric layer and the interlayer dielectric at the first end and the second end;
- a first conductive layer over the gate dielectric layer, wherein the gate spacer is interposed between the first conductive layer and the interlayer dielectric at the first end, wherein a distance from the first fin to an end of the first conductive layer is less than a distance from the second fin to the end of the first conductive layer;
- a second conductive layer over the gate dielectric layer, wherein the gate spacer is interposed between the second conductive layer and the interlayer dielectric at the first end, wherein a distance from the first fin to an end of the second conductive layer is greater than a distance from the second fin to the end of the second conductive layer;
- and
- a third conductive layer over the second conductive layer, wherein an upper surface of the third conductive layer is level with an upper surface of the interlayer dielectric.
Dependencies are inferred from the claim text.