Integrated circuit structure with niobium-based silicide layer and methods to form same
AssigneeGlobalFoundries U.S. Inc.
InventorsWei Hong, Yanping Shen, Domingo A. Ferrer, Hong Yu
Life of this patent
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Abstract
Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.
Claims12
An integrated circuit (IC) structure, comprising:
- a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure;
- a niobium-based silicide layer on at least an upper surface the S/D region of the transistor, wherein the niobium-based silicide layer extends across substantially an entire width of the S/D region;
- an S/D contact to the S/D region and in contact with the niobium-based silicide layer, wherein a bottom surface of the S/D contact is in contact with the S/D region and wherein a sidewall of the S/D contact is in contact with the niobium-based silicide layer;
- and
- an insulative liner on an upper surface of the niobium-based silicide layer and an upper surface of the gate structure, and in contact with each of a sidewall of the gate structure and the sidewall of the S/D contact.
An integrated circuit (IC) structure, comprising:
- a first transistor on a substrate, the first transistor including a first gate structure above the substrate and a first source/drain (S/D) region on the substrate adjacent the first gate structure;
- a niobium-based silicide layer on at least an upper surface the first S/D region of the first transistor, wherein the niobium-based silicide layer extends across substantially an entire width of the first S/D region;
- an isolation layer on the substrate adjacent the first transistor;
- an second transistor on the substrate adjacent the isolation layer, the second transistor including a second gate structure above the substrate and a second source/drain (S/D) region on the substrate adjacent the second gate structure, wherein the isolation layer is between the first transistor and the second transistor, and wherein the second S/D region is free of niobium-based silicide material thereon;
- a first S/D contact to the first S/D region in contact with the niobium-based silicide layer, wherein a bottom surface of the first S/D contact is in contact with the first S/D region and wherein a sidewall of the first S/D contact is in contact with the niobium-based silicide layer;
- a second S/D contact to the second S/D region in contact with the second S/D region;
- and
- an insulative liner on an upper surface of the niobium-based silicide layer, an upper surface of the first gate structure, an upper surface of the second gate structure, and in contact with each of a sidewall of the first gate structure, a sidewall of the second gate structure, and the sidewall of the first S/D contact.
Dependencies are inferred from the claim text.