US 11,239,335 B2Granted

Structure and method for semiconductor devices

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorJhon Jhy Liaw

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Abstract

The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a semiconductor substrate having a top surface;
a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate;
a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature, the second semiconductor layer extending longitudinally in the first direction and connecting the first source/drain feature and the second source/drain feature, wherein the first semiconductor layer is stacked over and spaced apart the second semiconductor layer in a second direction perpendicular to the first direction, the second direction being normal to the top surface of the semiconductor substrate;
and
a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer, wherein a length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction, and wherein a width of the first semiconductor layer is different from a width of the second semiconductor layer, wherein each of the width of the first semiconductor layer and the width of the second semiconductor layer is measured in a third direction perpendicular to the first direction and the second direction.

2 more elements

An integrated circuit (IC) device, comprising:

a semiconductor substrate having a top surface;
a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate;
a plurality of semiconductor layers extending from the first source/drain feature to the second source/drain feature along a first direction, the plurality of semiconductor layers stacked over each other along a second direction normal to the top surface and perpendicular to the first direction, wherein each of the semiconductor layers has a center portion and two side portions laterally adjacent to the center portion;
a gate electrode engaging the center portion of each of the semiconductor layers;
a first spacer over the two side portions of a topmost semiconductor layer of the semiconductor layers;
and
a second spacer between vertically adjacent side portions of the semiconductor layers along the second direction, wherein:
the first spacer includes a first dielectric material having a first dielectric constant;
the second spacer includes a second dielectric material having a second dielectric constant different from the first dielectric constant;
and
a length of the topmost semiconductor layer, as measured along the first direction, is smaller than a length of each of the semiconductor layers vertically below the topmost semiconductor layer.

8 more elements

An integrated circuit (IC) device, comprising:

a semiconductor substrate having a top surface;
a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate;
a plurality of semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature, wherein the semiconductor layers are stacked over and spaced apart from each other in a second direction perpendicular to the first direction, the second direction being normal to the top surface of the semiconductor substrate;
a gate structure engaging center portions of the semiconductor layers, wherein the semiconductor layers include respective lengths along the first direction, wherein the respective lengths are different from each other;
a first spacer disposed over side portions of the top semiconductor layer;
and
a second spacer disposed between the side portions of the top semiconductor layer and side portions of the middle semiconductor layer in the first direction, wherein the first spacer and the second spacer have different material compositions.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/585,636Filed 27 Sep 2019
Published: US 2021/0098627 A11 Apr 2021
Granted: 1 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around
H10D 30/0194
Forming stacked channels, e.g. changing their shapes or sizes: the stacked channels having different properties
H10D 30/0196
Forming inner spacers between adjacent channels, e.g. changing their shapes or sizes: by modifying properties of the inner spacers
H10D 30/0197
Forming inner spacers between adjacent channels, e.g. changing their shapes or sizes: the inner spacers having different properties