Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoon Tae Hwang, Wandon Kim, Geunwoo Kim
Life of this patent
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Abstract
A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.
Claims19
A semiconductor device, comprising:
- a lower contact pattern including a first metal;
- an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal;
- a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals;
- a semiconductor layer;
- an interlayer dielectric layer on the semiconductor layer;
- and
- a conductive line on the interlayer dielectric layer,
- wherein the lower contact pattern is in the semiconductor layer,
- wherein the upper contact pattern penetrates the interlayer dielectric layer and connects the conductive line to the lower contact pattern, and
- wherein a lower width of the upper contact pattern is less than an upper width of the lower contact pattern.
A semiconductor device, comprising:
- a semiconductor substrate;
- an interlayer dielectric layer on the semiconductor substrate;
- a conductive line on the interlayer dielectric layer;
- an upper contact pattern penetrating the interlayer dielectric layer, the upper contact pattern including a first metal;
- a lower contact pattern surrounding a lower portion of the upper contact pattern, the lower contact pattern including a second metal, the second metal being different from the first metal;
- and
- a metal barrier layer between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer including a third metal different from the first and second metals,
- wherein the lower contact pattern has a first upper width and a first lower width less than the first upper width,
- wherein the upper contact pattern has a second upper width and a second lower width, both of which are less than the first lower width,
- wherein a bottom surface of the upper contact pattern is between a top and a bottom of the lower contact pattern,
- wherein the lower contact pattern is in the semiconductor substrate, and
- wherein the upper contact pattern penetrates the interlayer dielectric layer and connects the conductive line to the lower contact pattern.
A semiconductor device, comprising:
- a semiconductor substrate including an active pattern;
- a gate structure running across the active pattern and extending in a first direction;
- a plurality of source/drain patterns on the active pattern, each of the source/drain patterns being on opposite sides of the gate structure;
- and
- a contact structure coupled to a corresponding one of the source/drain patterns,
- wherein the contact structure includes,
- a lower contact pattern in the corresponding one of the source/drain patterns, the lower contact pattern including a first metal,
- an upper contact pattern including a lower portion that is in a recess defined by a top surface of the lower contact pattern, the upper contact pattern including a second metal, and
- a metal barrier layer between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer including a third metal, and
- wherein a bottom of the upper contact pattern is lower than a top of the lower contact pattern.
Dependencies are inferred from the claim text.