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US 11,239,331 B2Granted
Thin film transistor substrate and method of fabricating same
OwnerQian Ma, Xingyu Zhouinventors
Life of this patent
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Abstract
A thin film transistor substrate and a method of fabricating same are provided. The thin film transistor substrate includes a substrate, a light shielding layer disposed on the substrate, a buffer layer disposed on the light shielding layer, an active layer disposed on the buffer layer, and a gate insulating layer disposed on the active layer. The gate insulating layer includes a stacked structure including a first insulating layer and a second insulating layer.
Claims4
A method of fabricating a thin film transistor substrate, comprising steps of:
- S1, providing a substrate, sequentially forming a light shielding layer, a buffer layer, and an active layer on the substrate;
- S2, forming a gate insulating layer on the active layer, wherein the gate insulating layer comprises a stacked structure comprising a first insulating layer and a second insulating layer, a thickness of the first insulating layer is not less than a thickness of the second insulating layer, and the second insulating layer is disposed on the first insulating layer;
- S3, sequentially forming a metal layer and a photoresist layer on the gate insulating layer;
- S4, etching the metal layer by using the photoresist layer as an occlusion to obtain a gate layer, and removing a portion of the metal layer that is not blocked by the photoresist layer;
- S5, etching the gate insulating layer by self-aligning the gate layer, and performing a conductor treatment, wherein the active layer not blocked by the gate insulating layer forms a conductor layer;
- S6, after the gate insulating layer is etched and the conductor treatment is completed, the photoresist layer is stripped;
- S7, forming an interlayer insulating layer on the gate layer;
- S8, opening at least one hole in the interlayer insulating layer and the buffer layer to form at least one via hole;
- S9, forming a source/drain metal layer in the at least one via hole;
- and
- S10, forming a passivation layer on the source/drain metal layer;
- wherein the at least one via hole is formed by a yellow light process, the at least one via hole comprises a first via hole, a second via hole, and a third via hole, the first via hole is connected to a first conductor layer through the interlayer insulating layer, the second via hole is connected to a second conductor layer through the interlayer insulating layer, and the third via hole is connected to the light shielding layer through the interlayer insulating layer and the buffer layer sequentially.
9 more elements
Dependencies are inferred from the claim text.