Semiconductor device having interfacial layer and high κ dielectric layer

A device comprising:

• a core transistor comprising:
• a first channel region;
• a first gate stack over the first channel region, wherein the first gate stack comprises:
• a first silicon germanium oxide layer over the first channel region, wherein the first silicon germanium oxide layer has a first silicon-to-germanium ratio;
• a high-κ dielectric layer over the first silicon germanium oxide layer;
• and
• a first gate electrode over the high-κ dielectric layer, wherein a top of the first silicon germanium oxide layer is lower than a bottom of the high-κ dielectric layer;
• and
• first source and drain features, wherein the first channel region is between the first source and drain structures;
• and
• an input/output(I/O) transistor comprising:
• a second channel region;
• a second gate stack over the second channel region, wherein the second gate stack comprises:
• a second silicon germanium oxide layer over the second channel region, wherein the second silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio;
• and
• a second gate electrode over the second silicon germanium oxide layer;
• and
• second source and drain features, wherein the second channel region is between the second source and drain features.

A method, comprising:

• forming a first gate trench and a second gate trench that respectively exposes a first channel region and a second channel region of a semiconductive layer;
• forming a first dielectric layer and a second dielectric layer respectively over the first channel region and the second channel region of the semiconductive layer;
• removing the first dielectric layer from the first channel region of the semiconductive layer, wherein the second dielectric layer remains over the second channel region of the semiconductive layer after removing the first dielectric layer;
• after removing the first dielectric layer, heating at least the first channel region of the semiconductive layer in an oxygen-containing environment in a process chamber;
• transferring the semiconductive layer from the process chamber to a cooling plate out of the process chamber;
• spreading, by the cooling plate, a coolant at a backside of the semiconductive layer;
• and
• after heating at least the first channel region of the semiconductive layer in the oxygen-containing environment, forming a first replacement gate feature in the first gate trench and a second replacement gate feature in the second gate trench.