Semiconductor memory device capable of suppressing leakage current

A semiconductor device comprising:

• a first conductivity-type semiconductor substrate comprising a crushed layer on a back side surface thereof;
• a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer;
• and
• a first conductivity-type high voltage transistor disposed on the semiconductor substrate, the first conductivity-type high voltage transistor including a first conductivity-type channel, the first conductivity-type high voltage transistor configured to supply a high voltage to the memory cell array, wherein the first conductivity-type high voltage transistor comprises:
• a well region disposed on the front side surface, the well region having a conductivity type which is a second conductivity type opposite to the first conductivity type;
• a first conductivity-type source region and a first conductivity-type drain region disposed in the well region;
• a first conductivity-type first high concentration layer disposed between the crushed layer and the well region, the first high concentration layer having a higher concentration than an impurity concentration of the semiconductor substrate;
• a selected block node;
• and
• a level shifter configured to supply a high voltage to the memory cell array through the selected block node, wherein the level shifter comprises,
• the first conductivity-type high voltage transistor,
• a second conductivity-type second high voltage transistor comprising a source connected to a source of the first conductivity-type high voltage transistor and the well region, a drain to which a high voltage is supplied, and a gate connected to a drain of the first conductivity-type high voltage transistor and the selected block node, and
• a second conductivity-type first high voltage transistor comprising a source connected to the drain of the first conductivity-type high voltage transistor and the selected block node, and a drain connected an outside, the second conductivity-type first high voltage transistor configured to drive the second conductivity-type second high voltage transistor.