Integrated chip and method of forming thereof

An integrated chip, comprising:

• an isolation structure arranged within a substrate and defining a continuous active region in the substrate;
• a first doped region disposed within the continuous active region;
• a second doped region disposed within the continuous active region and separated from the first doped region by a middle region of the continuous active region along a first direction, wherein the first doped region has a first width along a second direction perpendicular to the first direction, the second doped region has a second width along the second direction, and the middle region has a third width along the second direction and greater than the first width or the second width;
• and
• a gate structure extending over the continuous active region along the second direction, the gate structure comprising a first gate electrode region having a first work function and a plurality of second gate electrode regions having second work functions different from the first work function, the plurality of second gate electrode regions are separated by a center portion of the first gate electrode region, and that the first gate electrode region and the second gate electrode regions have top surfaces coplanar from one another.

An integrated chip, comprising:

• a source region and a drain region disposed in a substrate;
• a channel region arranged between the source region and the drain region along a first direction and extending past the source region and the drain region along a second direction perpendicular to the first direction, wherein the source region, the drain region, and the channel region are semiconductor bodies having boundaries limited and defined by an isolation structure;
• and
• a gate structure overlying and covering a top surface of the channel region;
• wherein the source region has a first width along the second direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and greater than the first width or the second width,
• wherein the gate structure comprises a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials, wherein the first gate electrode region and the second gate electrode region are arranged one next to another laterally along the second direction.