US 11,239,268 B2Granted

Electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsTakeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura

Life of this patent

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Abstract

An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

Claims20

Dependent claims

A solid-state imaging device comprising:

a first pixel;
and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises:
a photodiode;
a first wire electrically connected to an anode of the photodiode;
a second wire electrically connected to the first wire;
a first transistor, wherein a gate of the first transistor is electrically connected to a third wire, one of a source and a drain of the first transistor is electrically connected to a cathode of the photodiode, and the other of the source and the drain of the first transistor is electrically connected to a fourth wire;
a second transistor, wherein a gate of the second transistor is electrically connected to the fourth wire, and one of a source and a drain of the second transistor is electrically connected to a fifth wire;
and
a third transistor, wherein a gate of the third transistor is electrically connected to a sixth wire, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a seventh wire,
wherein the first wire intersects with the second wire,
wherein, in a plan view, the first wire comprises a convex portion,
wherein, in a plan view, the convex portion and the anode overlap with each other,
wherein the fourth wire is provided in a same layer as the first wire and the fifth wire,
wherein, in a plan view, the fourth wire is provided between the first wire and the fifth wire,
wherein the second wire is provided in a same layer as the third wire and the sixth wire,
wherein the fifth wire intersects with the second wire, the third wire, and the sixth wire, and
wherein a wire with a fixed potential is provided between the second pixel and the fourth wire of the first pixel.

16 more elements

A solid-state imaging device comprising:

a first pixel;
and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises:
a photodiode;
a first wire electrically connected to an anode of the photodiode;
a second wire electrically connected to the first wire;
a first transistor, wherein a gate of the first transistor is electrically connected to a third wire, one of a source and a drain of the first transistor is electrically connected to a cathode of the photodiode, and the other of the source and the drain of the first transistor is electrically connected to a fourth wire;
a second transistor, wherein a gate of the second transistor is electrically connected to the fourth wire, and one of a source and a drain of the second transistor is electrically connected to a fifth wire;
and
a third transistor, wherein a gate of the third transistor is electrically connected to a sixth wire, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a seventh wire,
wherein the first wire intersects with the second wire,
wherein, in a plan view, the first wire comprises a convex portion,
wherein, in a plan view, the convex portion and the anode overlap with each other,
wherein the fourth wire is provided in a same layer as the first wire and the fifth wire,
wherein, in a plan view, the fourth wire is provided between the first wire and the fifth wire,
wherein the second wire is provided in a same layer as the third wire and the sixth wire,
wherein the fifth wire intersects with the second wire, the third wire, and the sixth wire, and
wherein a wire with a fixed potential is provided between a wire whose potential changes of the second pixel and the fourth wire of the first pixel.

16 more elements

A solid-state imaging device comprising:

a first pixel;
and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises:
a photodiode;
a first wire electrically connected to an anode of the photodiode;
a second wire electrically connected to the first wire;
a first transistor, wherein a gate of the first transistor is electrically connected to a third wire, one of a source and a drain of the first transistor is electrically connected to a cathode of the photodiode, and the other of the source and the drain of the first transistor is electrically connected to a fourth wire;
a second transistor, wherein a gate of the second transistor is electrically connected to the fourth wire, and one of a source and a drain of the second transistor is electrically connected to a fifth wire;
and
a third transistor, wherein a gate of the third transistor is electrically connected to a sixth wire, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a seventh wire,
wherein the first wire intersects with the second wire,
wherein, in a plan view, the first wire comprises a convex portion,
wherein, in a plan view, the convex portion and the anode overlap with each other,
wherein the fourth wire is provided in a same layer as the first wire and the fifth wire,
wherein, in a plan view, the fourth wire is provided between the first wire and the fifth wire,
wherein the second wire is provided in a same layer as the third wire and the sixth wire,
wherein the fifth wire intersects with the second wire, the third wire, and the sixth wire, and
wherein a power supply line is provided between the second pixel and the fourth wire of the first pixel.

16 more elements

A solid-state imaging device comprising:

a first pixel;
and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises:
a photodiode;
a first wire electrically connected to an anode of the photodiode;
a second wire electrically connected to the first wire;
a first transistor, wherein a gate of the first transistor is electrically connected to a third wire, one of a source and a drain of the first transistor is electrically connected to a cathode of the photodiode, and the other of the source and the drain of the first transistor is electrically connected to a fourth wire;
a second transistor, wherein a gate of the second transistor is electrically connected to the fourth wire, and one of a source and a drain of the second transistor is electrically connected to a fifth wire;
and
a third transistor, wherein a gate of the third transistor is electrically connected to a sixth wire, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a seventh wire,
wherein the first wire intersects with the second wire,
wherein, in a plan view, the first wire comprises a convex portion,
wherein, in a plan view, the convex portion and the anode overlap with each other,
wherein the fourth wire is provided in a same layer as the first wire and the fifth wire,
wherein, in a plan view, the fourth wire is provided between the first wire and the fifth wire,
wherein the second wire is provided in a same layer as the third wire and the sixth wire,
wherein the fifth wire intersects with the second wire, the third wire, and the sixth wire, and
wherein a power supply line is provided between a wire whose potential changes of the second pixel and the fourth wire of the first pixel.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/902,124Filed 15 Jun 2020 · continuation
Priority: JP 2010-1989286 Sep 2010
Published: US 2021/0082976 A118 Mar 2021
Granted: 1 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10F 39/802
Constructional details of image sensors: geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
G09G 3/3648
Control of matrices with row and column drivers: using an active matrix
H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10F 39/18
Image sensors: complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Family

Application13/224,655Parent of this division · filed 2 Sep 2011
Application14/990,934Parent of this continuation · filed 8 Jan 2016
US 9,252,171 B2Parent of this division · filed 2 Feb 2016
Application16/161,209Parent of this continuation · filed 16 Oct 2018
US 10,109,661 B2Parent of this continuation · filed 23 Oct 2018
US 2021/0082976 A1Pre-grant publication · published 18 Mar 2021
US 10,685,992 B2Parent of this continuation
Application14/990,934Parent of this division
US 2012/0056252 A1Published application
US 2016/0126270 A1Published application
US 2019/0051683 A1Published application
US 11,239,268 B2This patent

From the US filing history. Foreign family members aren’t listed.