Substrate, manufacturing method thereof and transparent display device
AssigneeBoe Technology Group Co., Ltd.
InventorsHongda Sun, Fengjuan Liu, Dini Xie, Pengfei Gu
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Abstract
The present disclosure provides a substrate, a manufacturing method thereof, and a transparent display device. The substrate comprising: a plurality of pixel units, at least a part of which includes a light-emitting area and a transparent area, and the light-emitting area includes a thin-film transistor; a light blocking member disposed in the light-emitting area and configured to block light that is directed to the thin-film transistor through the transparent area.
Claims13
A substrate comprising:
- a plurality of pixel units, at least a part of which includes a light-emitting area and a transparent area, and the light-emitting area includes a thin-film transistor;
- a light blocking member disposed in the light-emitting area and configured to block light that is directed to the thin-film transistor through the transparent area,
- wherein the light blocking member includes a reflective layer, the thin-film transistor includes a plurality of insulating layers, and the reflective layer covers at least a part of the plurality of insulating layers on a side thereof facing the transparent area,
- wherein the light blocking member further comprises an ultraviolet blocking wall, the ultraviolet blocking wall is located in the light-emitting area, and the ultraviolet blocking wall is located on a side of the reflective layer near the transparent area, and
- wherein the light-emitting area further comprises a planarization layer covering the thin-film transistor and the reflective layer, and at least a part of the planarization layer constitutes the ultraviolet blocking wall,
- wherein a barrier wall is further provided in the light-emitting area, the barrier wall is located on the side of the reflective layer near the transparent area, and the ultraviolet blocking wall is located in a gap between the reflective layer and the barrier wall,
- the barrier wall comprises a first sublayer, a second sublayer, and a third sublayer from bottom to top,
- wherein the first sublayer and a buffer layer in the thin-film transistor are formed by a patterning process;
- the second sublayer and a gate insulation layer in the thin-film transistor are formed by a patterning process;
- and
- the third sublayer and an interlayer insulating layer in the thin-film transistor are formed by a patterning process.
A transparent display device comprising a substrate, the substrate comprising:
- a plurality of pixel units, at least a part of which includes a light-emitting area and a transparent area, and the light-emitting area includes a thin-film transistor;
- a light blocking member disposed in the light-emitting area and configured to block light that is directed to the thin-film transistor through the transparent area,
- wherein the light blocking member includes a reflective layer, the thin-film transistor includes a plurality of insulating layers, and the reflective layer covers at least a part of the plurality of insulating layers on a side thereof facing the transparent area,
- the light blocking member further comprises an ultraviolet blocking wall, the ultraviolet blocking wall is located in the light-emitting area, and the ultraviolet blocking wall is located on a side of the reflective layer near the transparent area, and
- the light-emitting area further comprises a planarization layer covering the thin-film transistor and the reflective layer, and at least a part of the planarization layer constitutes the ultraviolet blocking wall,
- wherein a barrier wall is further provided in the light-emitting area, the barrier wall is located on the side of the reflective layer near the transparent area, and the ultraviolet blocking wall is located in a gap between the reflective layer and the barrier wall,
- the barrier wall comprises a first sublayer, a second sublayer, and a third sublayer from bottom to top,
- wherein the first sublayer and a buffer layer in the thin-film transistor are formed by a patterning process;
- the second sublayer and a gate insulation layer in the thin-film transistor are formed by a patterning process;
- and
- the third sublayer and an interlayer insulating layer in the thin-film transistor are formed by a patterning process.
A method for manufacturing a substrate, the substrate comprising a plurality of pixel units, at least a part of which includes a light-emitting area and a transparent area, and the light-emitting area includes a thin-film transistor;
- a light blocking member disposed in the light-emitting area and configured to block light that is directed to the thin-film transistor through the transparent area,
- the method comprising:
- forming the plurality of pixel units;
- wherein forming at least a part of the plurality of pixel units includes forming the thin-film transistor and the light blocking member in the light-emitting area,
- wherein the light blocking member includes a reflective layer, the thin-film transistor includes a plurality of insulating layers, and the reflective layer covers at least a part of the plurality of insulating layers on a side thereof facing the transparent area,
- wherein the light blocking member further comprises an ultraviolet blocking wall, the ultraviolet blocking wall is located in the light-emitting area, and the ultraviolet blocking wall is located on a side of the reflective layer near the transparent area, and
- wherein forming at least a part of the plurality of pixel units further comprises a step of forming a planarization layer, and a part of the planarization layer is filled in a gap between the reflective layer and a barrier wall, and the part of the planarization layer filled in the gap constitutes the ultraviolet blocking wall,
- wherein the barrier wall is further provided in the light-emitting area, the barrier wall is located on the side of the reflective layer near the transparent area, and the ultraviolet blocking wall is located in a gap between the reflective layer and the barrier wall,
- the barrier wall comprises a first sublayer, a second sublayer, and a third sublayer from bottom to top,
- wherein the first sublayer and a buffer layer in the thin-film transistor are formed by a patterning process;
- the second sublayer and a gate insulation layer in the thin-film transistor are formed by a patterning process;
- and
- the third sublayer and an interlayer insulating layer in the thin-film transistor are formed by a patterning process.
Dependencies are inferred from the claim text.