US 11,239,252 B2Granted

Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

AssigneeMicron Technology, Inc.

InventorsJustin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park

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Abstract

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Claims6

Dependent claims

An integrated structure, comprising:

a vertically-stack comprising conductive levels alternating with dielectric levels;
vertically-stacked NAND memory cells along the conductive levels within a memory array region;
a silicon nitride material over the memory array region, the material being separated by an uppermost of the conductive levels by an intervening insulative material;
the silicon nitride material comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus;
a first opening within the memory array region extending through the silicon nitride material over the memory array region and through at least some of the vertically-stacked conductive levels;
a channel material within the first opening;
and
a second opening spaced from the first opening by regions of the stack, the second opening having sidewalls comprising the silicon nitride material, the insulative material, conductive material of the conductive levels and dielectric material of the dielectric levels, the second opening subdividing the memory array region into programmable blocks.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/907,967Filed 22 Jun 2020 · continuation
Priority: 19 Apr 2016
Published: US 2020/0321352 A18 Oct 2020
Granted: 1 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10W 20/4441
The principal metal being a transition metal: the principal metal being a refractory metal

Family

Application15/133,119Parent of this continuation · filed 19 Apr 2016
Application16/158,039Parent of this continuation · filed 11 Oct 2018
US 10,157,933 B2Parent of this continuation · filed 18 Dec 2018
US 2020/0321352 A1Pre-grant publication · published 8 Oct 2020
US 10,720,446 B2Parent of this continuation
US 2017/0301685 A1Published application
US 2019/0043890 A1Published application
US 11,239,252 B2This patent

From the US filing history. Foreign family members aren’t listed.