Vertical-type memory device

A vertical-type memory device comprising:

• a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate, and a semiconductor layer disposed on the first gate electrodes;
• a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure;
• and
• channel structures penetrating through the first gate structure and the second gate structure and being in contact with the substrate,
• wherein the semiconductor layer includes first semiconductor regions and second semiconductor regions extending in a first direction parallel to an upper surface of the substrate and alternately disposed in a second direction intersecting the first direction,
• wherein the first semiconductor regions are doped with impurities having a conductivity type different from that of impurities doped in the second semiconductor regions, and
• wherein each of the channel structures penetrates through the semiconductor layer with one side surface being in contact with one of the first semiconductor regions, and an other side surface being in contact with one of the second semiconductor regions.

A vertical-type memory device comprising:

• a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate, and a semiconductor layer disposed on the first gate electrodes;
• a first channel structure penetrating through the first gate structure and being in contact with the substrate;
• a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure;
• and
• a second channel structure penetrating through the second gate structure and being in contact with the first channel structure,
• wherein the first gate structure includes a first channel layer penetrating the first gate structure, and an insulating layer positioned at a level the same as a level of the semiconductor layer, and locally disposed on an internal side surface of the first channel layer,
• wherein the insulating layer is spaced apart from the second channel structure, and
• wherein the first channel structure includes a channel pad covering the insulating layer and the first channel layer.