Cell boundary structure for embedded memory

A method for forming an integrated circuit (IC) comprising:

• forming a memory cell on a semiconductor substrate in a memory region;
• forming an isolation structure separating the memory region and a logic region, the isolation structure comprising a dielectric material;
• forming a dummy control gate structure on the isolation structure, wherein the dummy control gate structure defines a dummy sidewall that faces the logic region and that comprises multiple different materials;
• forming a boundary sidewall spacer on the isolation structure along and directly contacting the dummy sidewall of the dummy control gate structure;
• and
• forming a logic device on the logic region;
• wherein the dummy sidewall is made to have an upper vertical portion and a lower vertical portion connected by a lateral portion, wherein the upper vertical portion is recessed toward the memory region relative to the lower vertical portion.

A method for forming an integrated circuit (IC), the method comprising:

• forming an isolation structure separating a logic region and a memory region of a substrate;
• forming and patterning a lower pad layer and an upper pad layer in the logic region;
• forming a precursor oxide layer in the memory region from a top surface of the substrate and reducing a height of the top surface of the memory region using the upper pad layer as a mask;
• forming a dummy structure on the isolation structure;
• and
• forming a boundary sidewall spacer covering the dummy structure.