Etch method for opening a source line in flash memory

An integrated circuit (IC) comprising:

• a substrate;
• a memory array comprising a plurality of cells, wherein the plurality of cells comprises a source strap cell and a pair of control gate strap cells;
• an erase gate line and a source line partially defining the source strap cell and elongated in parallel in a first direction, wherein the source line underlies the erase gate line, and wherein the erase gate line has a first break in the first direction;
• a first control gate line, a second control gate line, and a pair of select gate lines partially defining the control gate strap cells and elongated in parallel in the first direction, wherein the select gate lines are between and respectively border the first and second control gate lines and have a second break in the first direction, and wherein the first control gate line has a pad protruding towards the second control gate line at the second break;
• and
• a trench isolation structure underlying the first and second control gate lines;
• wherein a top of the substrate has a recess with a U-shaped top layout that wraps around the pad at the second break.

A memory device comprising:

• a substrate;
• an erase gate line and a control gate line that are elongated in parallel in a first direction, wherein the erase gate line has a break separating the erase gate line into a pair of erase gate segments bordering in the first direction, and wherein the control gate line borders the erase gate line;
• a source line underlying the erase gate line in the substrate;
• a source dielectric layer separating the erase gate line and the source line;
• an etch stop layer (ESL) laterally and directly contacting a sidewall of the source dielectric layer at a center between the erase gate segments and having a top surface level with the control gate line;
• and
• a contact via extending through the erase gate line, the ESL, and the source dielectric layer at the break, wherein the contact via laterally and directly contacts a sidewall of the ESL and is electrically coupled with the source line.