Partial buried insulator nano-sheet device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKam-Tou Sio, Yi-Hsun Chiu
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Abstract
Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.
Claims20
A semiconductor device comprising:
- a source region and a drain region formed above a substrate;
- a buried insulator (BI) layer formed beneath only one of the source region or the drain region and above the substrate;
- and
- a first nano-sheet formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer.
A static random access memory (SRAM) device comprising:
- a plurality of SRAM bitcells, each SRAM bitcell comprising:
- a portion of a buried insulator (BI) layer formed beneath only a first source/drain region;
- a plurality of nano-sheet layers separating the first source/drain region from a second source/drain region;
- and
- a bitline coupling together the plurality of the SRAM bitcells, the bitline electrically coupled to the portion of the BI layer.
A method comprising:
- forming a first nano-sheet above a substrate;
- depositing a first gate electrode layer above the first nano-sheet;
- forming a buried insulator (BI) layer above the substrate;
- and
- forming only one of a source region or a drain region above the BI layer, wherein the first nano-sheet is positioned (i) horizontally between the source region or the drain region and (ii) vertically above the BI layer.
Dependencies are inferred from the claim text.