Thin film transistor based memory cells on both sides of a layer of logic devices

A method of fabricating an integrated circuit (IC) device, the method comprising:

• forming logic devices in a first layer over a first face of a support structure;
• forming a first memory cell in a second layer over the first face of the support structure, so that the first layer is between the first face of the support structure and the second layer;
• and
• forming a second memory cell in a third layer over a second face of the support structure, so that the support structure is between the third layer and the first layer.

An integrated circuit (IC) device, comprising:

• a first memory cell in a first layer attached to a support structure;
• and
• a second memory cell in a second layer attached to the support structure, wherein the support structure is between the first layer and the second layer;
• wherein:
• the first memory cell includes a thin-film transistor (TFT), and
• a word-line is coupled to a gate electrode of the TFT, a capacitor is coupled to a first one of a source electrode and a drain electrode of the TFT, and a bit-line is coupled to a second one of the source electrode and the drain electrode of the TFT.