Isolation walls for vertically stacked transistor structures

A method for forming an integrated circuit (IC), comprising:

• forming a first plurality of transistor structures at a lower device layer, the first plurality of transistor structures including a first transistor structure and a second transistor structure, and a first gap having a first gap width between the first transistor structure and the second transistor structure;
• forming a second plurality of transistor structures at an upper device layer above the lower device layer, the second plurality of transistor structures including a third transistor structure and a fourth transistor structure, and a second gap having a second gap width between the third transistor structure and the fourth transistor structure, wherein the second gap width is different from the first gap width;
• forming an insulating linear extending between the upper device layer and the lower device layer and conformally covering sidewalls of the first transistor structure, the second transistor structure, the third transistor structure, and the fourth transistor structure;
• and
• forming an isolation wall extending between the upper device layer and the lower device layer and filling the first gap between the first transistor structure and the second transistor structure, and the second gap between the third transistor structure and the fourth transistor structure.

A computing device, comprising:

• a circuit board;
• and
• an integrated circuit (IC) coupled to the circuit board, wherein the IC includes:
• a lower device layer that includes a first transistor structure, wherein the first transistor structure includes a first set of non-planar transistor body structure, a first gate structure, and a first gate dielectric layer to separate the first set of non-planar transistor body structure from the first gate structure;
• an upper device layer above the lower device layer, the upper device layer including a second transistor structure, wherein the second transistor structure includes a second set of non-planar transistor body structure, a second gate structure, and a second gate dielectric layer to separate the second set of non-planar transistor body structure from the second gate structure;
• and
• an isolation wall that extends between the upper device layer and the lower device layer, wherein the isolation wall is in contact with an edge of the first gate structure and an edge of the second gate structure, the isolation wall has a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer, and the first width is different from the second width;
• and
• the first gate structure has a first gate width between the edge of the first gate structure and an edge of the first gate dielectric layer, the second gate structure has a second gate width between the edge of the second gate structure and an edge of the second gate dielectric layer, and the first gate width and the second gate width are substantially equal.