IC with larger and smaller width contacts
AssigneeTexas Instruments Incorporated
InventorsAbbas Ali, Guruvayurappan Mathur, Poornika Fernandes
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.
Claims24
A method of fabricating an integrated circuit (IC), comprising:
- forming a first via through a first dielectric layer to a first conductive level over a semiconductor substrate, the first via having a first diameter;
- forming a second via through the first dielectric layer to a second conductive level located over the first conductive level and directly over a shallow trench isolation (STI) layer that touches the first dielectric layer, the second via having the first diameter;
- forming a third via through the first dielectric layer to a third conductive level located directly over the second conductive level, the third via having a second diameter different than the first diameter.
An integrated circuit (IC), comprising:
- first, second and third conductive levels located over a semiconductor substrate, the second conductive level located between the first and third conductive levels, and the first conductive level located between the second conductive level and the substrate and including a circuit element formed in a semiconductor layer over the substrate;
- a first dielectric layer located over the first, second and third conductive levels, and having a surface, the first dielectric layer touching a shallow trench isolation (STI) layer that is located within the semiconductor layer adjacent the circuit element;
- a first via that traverses the first dielectric layer from the surface to the first conductive level, the first via having a first diameter;
- a second via that traverses the first dielectric layer from the surface to the second conductive level, the second via having the first diameter;
- and
- a third via that traverses the first dielectric layer from the surface to the third conductive level, the third via having a second diameter different than the first diameter.
An integrated circuit (IC), comprising:
- a circuit level in or over a semiconductor substrate, the circuit level including at least one transistor;
- a capacitor formed over the semiconductor substrate and configured to implement a circuit function in cooperation with the at least one transistor, the capacitor including:
- a bottom plate comprising polysilicon located over a shallow trench isolation (STI) layer;
- a top plate comprising Ti, TiN or TaN;
- a capacitor dielectric between the top and bottom plates;
- a pre-metal dielectric (PMD) layer including silicon oxide located over the circuit level and the capacitor, and extending from the bottom plate toward the STI layer
- a first via through the PMD layer that electrically connects to the circuit level;
- a second via through the PMD layer that electrically connects to the bottom plate;
- and
- a third via through the PMD layer that electrically connects to the top plate,
- wherein the first and second vias each have a first diameter, and the third via has a second diameter larger than the first diameter.
An integrated circuit (IC), comprising:
- a first conductive level touching a semiconductor at a bottom of the first conductive level;
- a shallow trench isolation (STI) layer located in a trench within the semiconductor adjacent the first conductive level;
- a second conductive level over the STI layer;
- a third conductive level located between the second conductive level and the STI layer;
- a first via having a first diameter that traverses a dielectric layer and connects to the first conductive layer, the dielectric layer touching each of the second and third conductive layers and extending from the third conductive layer toward the STI layer;
- a second via having the first diameter that traverses the dielectric layer and connects to the third conductive layer;
- a third via having a second different diameter that traverses the dielectric layer and connects to the second conductive layer.
Dependencies are inferred from the claim text.