Self-biased bidirectional ESD protection circuit
AssigneeTexas Instruments Incorporated
InventorsAntonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
Life of this patent
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Abstract
Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
Claims20
An integrated circuit (IC), comprising:
- a pad connected to a protected node;
- a host circuit connected to the pad to receive a voltage signal from an external circuit;
- a bidirectional ESD protection structure connected between the protected node and a reference node;
- and
- a bias circuit to bias a control terminal of the bidirectional ESD structure at a voltage corresponding to a higher one of a first voltage of the protected node and a second voltage of the reference node.
An integrated circuit (IC), comprising:
- a protected node;
- a protected circuit connected to the protected node;
- a bidirectional ESD protection structure connected between the protected node and a reference node;
- and
- a control circuit configured to provide a control signal to a control terminal of the bidirectional ESD protection structure at a voltage corresponding to a higher one of a first voltage of the protected node and a second voltage of the reference node.
An integrated circuit (IC), comprising:
- a protected circuit connected to a protected node;
- a bidirectional ESD protection structure having a control terminal and being connected between the protected node and a reference node;
- and
- a first MOS transistor, including a first source connected directly to the control terminal, a first drain connected to the protected node, and a first gate connected to the reference node, and
- a second MOS transistor, including a second source connected directly to the control terminal, a second drain connected to the reference node, and a second gate connected to the protected node.
An integrated circuit (IC), comprising:
- a pad connected to a protected node;
- a host circuit connected to the pad to receive a voltage signal from an external circuit;
- a bidirectional ESD protection structure connected between the protected node and a reference node, the bidirectional ESD protection structure including:
- a first protection structure terminal connected to the protected node;
- a second protection structure terminal connected to the reference node;
- a first p doped region in a substrate;
- a first n+region and a first p+region formed in the first p doped region to define a first contact electrically connected to the first protection structure terminal;
- a second p doped region laterally spaced from the first p doped region in the substrate;
- a second n+region and a second p+region formed in the second p doped region to define a second contact electrically connected to the second protection structure terminal;
- a first n-well laterally disposed between the first and second p doped regions in the substrate;
- a deep n-well formed in the substrate beneath the first p doped region, and adjacent at least a portion of the first n-well to isolate the first and second contracts;
- a third p+region laterally disposed between the first n+region and the first n-well in the substrate;
- a fourth p+region laterally disposed between the second n+region and the first n-well in the substrate;
- and
- a gate structure formed above a channel region of the first n-well between the third and fourth p+regions to define a gate contact electrically connected to the control terminal;
- and
- a bias circuit to bias a control terminal of the bidirectional ESD structure at a voltage corresponding to a higher one of a first voltage of the protected node and a second voltage of the reference node.
Dependencies are inferred from the claim text.