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US 11,239,228 B2Granted
Integrated circuit layout and method of configuring the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
Claims20
An integrated circuit comprising:
- at least one first active area extending in a first direction;
- at least one second active area adjacent to the first active area, the at least one first active area and the at least one second active area being staggered relative to one another such that a first line in a second direction, orthogonal to the first direction, intersects both one first active area and one second active area and a second line in the second direction intersects one of but not both the one first active area and the one second active area;
- a gate electrode layer, the gate electrode layer having a first portion across the at least one first active area and a second portion extending in the second direction across the at least one second active area, the first and second portions being separated and physically spaced apart from one another;
- and
- a plurality of third active areas adjacent to the first active area.
2 more elements
An integrated circuit, comprising:
- a plurality of first cells;
- at least one second cell, wherein the at least one second cell is between each first cell of the plurality of first cells, and further wherein the at least one second cell has different circuits compared to respective first cells;
- each first cell having at least one first active area having a long axis and a short axis and at least one second active area, the at least one first active area and the at least one second active area being offset relative to one another along a direction parallel to the long axis;
- and
- each second cell having at least one third active area and at least one fourth active area, the at least one third active area and the at least one fourth active area being offset relative to one another along the direction parallel to the long axis.
2 more elements
An integrated circuit, comprising:
- two first cells, each first cell having active areas extending in a first longitudinal direction;
- a second cell between the first two cells, wherein said second cell has a different pattern of active areas relative said first cell;
- each first cell having at least one first active area and at least one second active area, the at least one first active area and the at least one second active area being staggered relative to one another in the first longitudinal direction;
- and
- said second cell having at least one third active area and at least one fourth active area, the at least one third active area and the at least one fourth active area being staggered relative to one another in the first longitudinal direction.
2 more elements
Dependencies are inferred from the claim text.