Semiconductor devices, methods of designing layouts of semiconductor devices and methods of fabricating semiconductor devices

A semiconductor device, comprising:

• a first hard macro;
• a second hard macro spaced apart from the first hard macro in a first direction by a first distance;
• a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell comprising a transistor configured to control whether a power supply voltage is applied to the first hard macro according to a control signal applied to a gate of the transistor;
• a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro;
• a substrate having an upper surface that extends in the first direction and a second direction that crosses the first direction;
• a signal connection layer provided on the upper surface;
• a power mesh layer provided on the signal connection layer;
• a via provided on the head cell and extending in a third direction through the signal connection layer to the power mesh layer, wherein the third direction is perpendicular to the upper surface and the power supply voltage applied to the first hard macro by the head cell is provided from the power mesh layer through the via;
• and
• a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro,
• wherein the head cell is interposed among the plurality of first ending cells adjacent the first hard macro, and does not overlap the plurality of first ending cells and the plurality of second ending cells,
• wherein each of the plurality of first ending cells is disposed along the second direction,
• wherein each of the plurality of second ending cells is disposed along the second direction, and
• wherein a first number of the plurality of first ending cells is less than a second number of the plurality of second ending cells.