Passive device module and semiconductor package including the same
AssigneeSamsung Electronics Co., Ltd.
InventorSanguk Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package including a lower redistribution layer including wiring patterns; a lower substrate on the lower redistribution layer, the lower substrate including a cavity; an application processor on the lower redistribution layer in the cavity; a cache memory chip on the application processor; a passive device module on the application processor; a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and lower bumps on a bottom surface of the lower redistribution layer, wherein the passive device module is adjacent to a side of the cache memory chip.
Claims17
A semiconductor package, comprising:
- a lower redistribution layer including wiring patterns;
- a lower substrate on the lower redistribution layer, the lower substrate including a cavity;
- an application processor on the lower redistribution layer in the cavity;
- a cache memory chip on the application processor;
- a passive device module on the application processor;
- a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module;
- and
- lower bumps on a bottom surface of the lower redistribution layer,
- wherein:
- the passive device module is adjacent to a side of the cache memory chip,
- the passive device module includes:
- a module substrate;
- at least one inductor on the module substrate;
- and
- a plurality of capacitors,
- the plurality of capacitors includes first capacitors disposed side-by-side in a first direction, and
- the at least one inductor surrounds the first capacitors.
A semiconductor package, comprising:
- a lower redistribution layer including a plurality of wiring patterns;
- a lower substrate on the lower redistribution layer, the lower substrate including a cavity;
- an application processor on the lower redistribution layer in the cavity;
- a cache memory chip on the application processor;
- a first passive device module on a top surface of the application processor and adjacent to a first edge of the application processor;
- a plurality of first through-silicon vias penetrating the application processor and electrically connecting the application processor to the first passive device module;
- a plurality of second through-silicon vias penetrating the application processor and electrically connecting the application processor to the cache memory chip;
- and
- lower bumps on a bottom surface of the lower redistribution layer,
- wherein:
- the first passive device module is adjacent to a first side of the cache memory chip,
- the first passive device module includes:
- a first module substrate;
- at least one first inductor on the first module substrate;
- and
- a plurality of first capacitors, and
- the at least one first inductor surrounds the plurality of first capacitors.
A semiconductor package, comprising:
- a lower package;
- an upper package stacked on the lower package;
- and
- a plurality of upper bumps configured to connect the lower package to the upper package,
- wherein the lower package includes:
- a lower redistribution layer including a plurality of wiring patterns;
- a lower substrate including a cavity;
- an application processor on the lower redistribution layer in the cavity;
- a cache memory chip on the application processor;
- a passive device module in a first region of a top surface of the application processor;
- and
- lower bumps on a bottom surface of the lower redistribution layer, and
- wherein:
- the passive device module is adjacent and parallel to at least one side surface of the cache memory chip,
- the passive device module includes:
- a module substrate;
- at least one inductor on the module substrate;
- and
- a plurality of capacitors, and
- the at least one inductor surrounds the plurality of capacitors.
Dependencies are inferred from the claim text.