US 11,239,207 B1Granted

Semiconductor die stacks and associated systems and methods

AssigneeMicron Technology, Inc.

InventorKyle K. Kirby

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Abstract

Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

Claims20

Dependent claims

A semiconductor die assembly, comprising:

a first semiconductor die including an array of memory cells, exclusive of circuitry configured to access the array of memory cells;
and
a second semiconductor die including complementary metal-oxide-semiconductor (CMOS) circuitry configured to access the array of memory cells of the first semiconductor die, wherein:
the first semiconductor die includes a first semiconductor substrate with a first thickness and the second semiconductor die includes a second semiconductor substrate with a second thickness different than the first thickness;
the first semiconductor die includes one or more first conductive components and a set of bond pads on a front side of the first semiconductor die, the first conductive components coupled with the array of memory cells;
the second semiconductor die includes one or more second conductive components on a front side of the second semiconductor die, the second conductive components coupled with the CMOS circuitry;
the second semiconductor die is arranged over the first semiconductor die such that each of the second conductive components is directly bonded to a corresponding one of the first conductive components;
and
an edge of the first semiconductor die extends past a corresponding edge of the second semiconductor die such that a portion of the front side of the first semiconductor die is exposed, the portion including the set of bond pads.

6 more elements

A semiconductor die assembly, comprising:

a first pair of dies including a first die attached to a second die, wherein a front surface of the first die and a front surface of the second dies are conjoined, and the front surface of the second die includes a first extended portion uncovered by the first die, the first extended portion including a first set of bond pads, and wherein the first die includes a first semiconductor substrate with a first thickness and the second die includes a second semiconductor substrate with a second thickness different than the first thickness;
a second pair of dies carried by the first pair of dies, the second pair including a third die attached to a fourth die, wherein a front surface of the third die and a front surface of the fourth dies are conjoined, and the front surface of the fourth die includes a second extended portion uncovered by the third die, the second extended portion including a second set of bond pads;
a support substrate, to which a back side of the second die of the first pair is attached, the support substrate including a plurality of substrate bond pads;
a plurality of first bond wires coupling individual ones of the first set of bond pads with corresponding individual ones of the plurality of substrate bond pads;
and
a plurality of second bond wires coupling individual ones of the second set of bond pads with corresponding individual ones of the plurality of substrate bond pads.

3 more elements

A method comprising:

providing a first die including an array of memory cells, exclusive of circuitry configured to access the array of memory cells;
providing a second die including complementary metal-oxide-semiconductor (CMOS) circuitry configured to access the array of memory cells of the first die, wherein the first die includes a first semiconductor substrate with a first thickness and the second die includes a second semiconductor substrate with a second thickness different than the first thickness;
conjoining the first and second dies to form a first pair of dies, wherein:
a front surface of the first die is in direct contact with a front surface of the second die, wherein the front surface of the first die includes a first extended portion uncovered by the second die, the first extended portion including a first set of bond pads;
and
the front surfaces of the first and second dies each includes a plurality of conductive components, each of the conductive components of the first die directly bonded to a corresponding one of the conductive components of the second die, and a first dielectric material surrounding each of the conductive components of the first die directly bonded to a second dielectric material surrounding the corresponding one of the conductive components of the second die;
and
attaching the first pair of dies to a support substrate including a plurality of substrate bond pads.

5 more elements

Dependencies are inferred from the claim text.