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US 11,239,199 B2Granted
Package stacking using chip to wafer bonding
AssigneeIntel Corporation
InventorsGeorg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
Life of this patent
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Abstract
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
Claims18
A device comprising:
- a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness;
- a second stacked layer including one or more semiconductor dies, components or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer, wherein the second dielectric layer is not vertically in between the one or more semiconductor dies, components or both of the first stacked layer and the one or more semiconductor dies, components or both of the second stacked layer;
- a first via bar in the first dielectric layer, the first via bar laterally spaced apart from a first lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the first via bar extends above a top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the first via bar does not extend below a bottom of the first dielectric layer;
- and
- a second via bar in the first dielectric layer, the second via bar laterally spaced apart from a second lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the second via bar extends above the top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the second via bar does not extend below the bottom of the first dielectric layer.
2 more elements
A stacked package comprising:
- a first stacked layer, wherein:
- the first stacked layer includes one or more semiconductor dies, components or both, and includes a first dielectric layer,
- the first stacked layer is thinned to a first thickness;
- and the first stacked layer comprising:
- a first via bar in the first dielectric layer, the first via bar laterally spaced apart from a first lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the first via bar extends above a top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the first via bar does not extend below a bottom of the first dielectric layer;
- and
- a second via bar in the first dielectric layer, the second via bar laterally spaced apart from a second lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the second via bar extends above the top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the second via bar does not extend below the bottom of the first dielectric layer;
- and
- one or more additional stacked layers, wherein:
- each additional stacked layer includes one or more semiconductor dies, components or both, and includes a dielectric layer, wherein the dielectric layer of a first of the additional stacked layers is not vertically in between the one or more semiconductor dies, components or both of the first stacked layer and the one or more semiconductor dies, components, or both of the first of the additional stacked layers, and
- each additional stacked layer is attached to a previous stacked layer by chip to wafer bonding, the previous stacked layer being thinned to a certain thickness;
- a metallization layer formed on a front side of the first stacked layer;
- and
- a ball grid array attached to the metallization layer.
11 more elements
A package, comprising:
- a die having a first side and a second side, the second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall;
- a first molding layer laterally adjacent to the first and second lateral sidewalls of the die, the first molding layer having an uppermost surface above the second side of the die;
- a first via bar in the first molding layer, the first via bar laterally spaced apart from the first lateral sidewall of the die, wherein the first via bar extends above the second side of the die, and wherein the first via bar does not extend below a bottom of the first molding layer;
- a second via bar in the first molding layer, the second via bar laterally spaced apart from the second lateral sidewall of the die, wherein the second via bar extends above the second side of the die, and wherein the second via bar does not extend below the bottom of the first molding layer;
- a component over the die, the component above the uppermost surface of the first molding layer, the component having a first side and a second side above the first side, and the component having a first lateral sidewall and a second lateral sidewall, wherein the first side of the component faces toward the die, and the second side of the component faces away from the die;
- a second molding layer laterally adjacent to the first and second lateral sidewalls of the component, and the second molding layer over the second side of the component, wherein the second molding layer is distinct from the first molding layer, wherein the second molding layer is not on the first side of the component;
- a first solder bump attached to the first via bar, the first solder bump electrically coupled to the component;
- and
- a second solder bump attached to the second via bar, the second solder bump electrically coupled to the component.
6 more elements
Dependencies are inferred from the claim text.