Chip package structure

A chip package structure, comprising:

• a first redistribution structure having a first surface and a second surface opposite to the first surface;
• a first chip over the first surface, wherein the first chip comprises a first substrate and a first conductive pad between the first substrate and the first redistribution structure;
• a first conductive pillar over the first surface and electrically connected to the wiring layers;
• a second chip over the second surface, wherein the second chip comprises a second substrate and a second conductive pad between the second substrate and the first redistribution structure;
• a second redistribution structure having a first top surface;
• a second conductive pillar over the first top surface and having a second top surface;
• a third chip over the first top surface and having a third top surface, wherein a first height of the second top surface relative to the first top surface is less than a second height of the third top surface relative to the first top surface;
• and
• a conductive bump connected between the second conductive pillar and the first conductive pillar.

A chip package structure, comprising:

• a redistribution structure comprising a dielectric layer and a wiring layer over and in the dielectric layer, wherein the redistribution structure has a first surface and a second surface opposite to the first surface, and a first width of the wiring layer in the dielectric layer decreases toward the second surface;
• a conductive pad over and in the dielectric layer, wherein a second width of the conductive pad in the dielectric layer decreases toward the first surface;
• a first chip over the first surface and connected to the wiring layer;
• a second chip over the second surface and connected to the conductive pad;
• and
• a conductive pillar over the second surface and connected to the wiring layer.