Semiconductor device and a method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorShinya Suzuki
Life of this patent
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Abstract
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
Claims26
A semiconductor device comprising:
- a semiconductor substrate having a long side and a short side;
- a multilayer wiring formed over the semiconductor substrate and including a first wiring formed in a top wiring layer of the multilayer wiring;
- a first dummy pattern formed in the top wiring layer;
- an insulating film formed over the first wiring and the first dummy pattern;
- a first bump electrode formed over the insulating film;
- and
- a second bump electrode formed over the insulating film,
- wherein, in plan view, the first bump electrode is adjacent to the second bump electrode in an extending direction of the long side of the semiconductor substrate,
- wherein, in plan view, the first bump electrode overlaps the first wiring but not the first dummy pattern,
- wherein, in plan view, the second bump electrode overlaps the first wiring and the first dummy pattern,
- wherein the first bump electrode has:
- a first short side;
- a second short side closer to the long side of the semiconductor substrate than the first short side in plan view;
- a first long side extending between the first short side and the second short side;
- and
- a second long side opposite to the first long side,
- wherein the second bump electrode has:
- a third short side;
- a fourth short side closer to the long side of the semiconductor substrate than the third short side in plan view;
- a third long side extending between the third short side and the fourth short side;
- and
- a fourth long side opposite to the third long side,
- wherein, in plan view and in an extending direction of the short side of the semiconductor substrate, each of the first wiring and the first dummy pattern is closer to the long side of the semiconductor substrate than each of the first short side of the first bump electrode and the third short side of the second bump electrode, and
- wherein, in plan view and in the extending direction of the short side of the semiconductor substrate, each of the first wiring and the first dummy pattern is further from the long side of the semiconductor substrate than each of the second short side of the first bump electrode and the fourth short side of the second bump electrode.
Dependencies are inferred from the claim text.