Embedded resistor-capacitor film for fan out wafer level packaging

A panel type fan out wafer level package with embedded film type capacitors and resistors comprising:

• only one silicon die at a bottom of said package wherein a top side and lateral sides of said silicon die are encapsulated in a molding compound;
• a bottomside solder protection mask on a bottom surface of said package wherein said bottomside solder protection mask directly contacts a bottom side of said silicon die;
• at least one redistribution layer connected to said silicon die through copper posts contacting said top side of said silicon die;
• copper through-mold vias interconnecting said at least one redistribution layer to solder balls attached to metal pads in openings through said bottomside solder protection mask on a bottom surface of said package;
• at least one embedded capacitor material (ECM) sheet laminated onto said package over said redistribution layer wherein aid a e ECM sheet comprises a diel layer sandwiched between copper foil layers;
• at least one embedded resistor-conductor material (RCM) sheet laminated onto said package over said redistribution layer wherein said at least one RCM sheet comprises a nickel phosphorus layer laminated to a overlying first copper foil layer and to an underlying dielectric layer wherein said dielectric layer is laminated to an underlying second copper foil layer, wherein copper-filled vias connect said ECM with said RCM, and wherein said copper posts, said at least one redistribution layer, capacitors in said at least one ECM, and resistors in said at least one RCM are electrically interconnected in said panel type fan out wafer level package;
• and
• a topside solder protection mask on a top surface of said package wherein said bottom side solder protection mask coats an entire bottom side of said silicon die.

A panel type fan out wafer level package with embedded film type capacitors and resistors comprising:

• only one silicon die at a bottom of said package wherein a top side and lateral sides of said silicon die are encapsulated in a molding compound;
• a bottomside solder protection mask on a bottom surface of said package wherein said bottomside solder protection mask directly contacts a bottom side of said silicon die;
• at least one copper post through said molding compound contacting said top side of said silicon die;
• at least one redistribution layer connected to said silicon die through said copper post;
• copper through-mold vias interconnecting said at least one redistribution layer to solder balls attached to metal pads in openings through said bottomside solder protection mask;
• at least one embedded capacitor material (ECM) sheet laminated onto said package over said redistribution layer wherein said at least one ECM sheet comprises a dielectric layer sandwiched between two copper foil layers;
• at least one embedded resistor-conductor material (RCM) sheet laminated onto said package over said redistribution layer wherein said at least one RCM sheet comprises a nickel phosphorus layer laminated to an overlying first copper foil layer and to an underlying dielectric layer wherein said dielectric layer is laminated to an underlying second copper foil layer, wherein copper filled vias connect said ECM with said RCM, and wherein said copper posts, said at least one redistribution layer, capacitors in said at least one ECM, and resistors in said at least one RCM are electrically interconnected in said panel type fan out wafer level package;
• and
• a topside solder protection mask on a top surface of said package wherein said bottomside solder protection mask coats an entire bottom side of said silicon die.