Chip package structure

A chip package structure, comprising:

• a first insulating layer having a first surface and a second surface opposite to each other;
• a first circuit structure disposed at the first surface;
• a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
• a second circuit structure disposed on the first chip and electrically connected to the top electrode;
• an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
• a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
• a second insulating layer disposed on the second circuit structure;
• a first heat dissipation layer disposed on the second surface;
• a second heat dissipation layer disposed on the second insulating layer;
• and
• a third circuit structure disposed on the second surface and electrically insulated from the first heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the first insulating layer and connected to the first circuit structure, the second circuit structure and the third circuit structure.

A chip package structure, comprising:

• a first insulating layer having a first surface and a second surface opposite to each other;
• a first circuit structure disposed at the first surface;
• a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
• a second circuit structure disposed on the first chip and electrically connected to the top electrode;
• an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
• a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
• a second insulating layer disposed on the second circuit structure;
• a first heat dissipation layer disposed on the second surface;
• a second heat dissipation layer disposed on the second insulating layer;
• and
• a fourth circuit structure disposed on the second insulating layer and electrically insulated from the second heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the second insulating layer and connected to the first circuit structure, the second circuit structure and the fourth circuit structure.

A chip package structure, comprising:

• a first insulating layer having a first surface and a second surface opposite to each other;
• a first circuit structure disposed at the first surface;
• a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
• a second circuit structure disposed on the first chip and electrically connected to the top electrode;
• an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
• a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
• a second insulating layer disposed on the second circuit structure;
• a first heat dissipation layer disposed on the second surface;
• a second heat dissipation layer disposed on the second insulating layer;
• and
• a second chip disposed on the first circuit structure, wherein the second chip has a top electrode, and the top electrode and the second circuit structure are electrically connected.