Semiconductor device including via and wiring

A semiconductor device comprising:

• a first via on a semiconductor substrate;
• a first wiring disposed on the first via and electrically connected to the first via;
• a second via on the first wiring and electrically connected to the first wiring;
• a second wiring on the second via and electrically connected to the second via;
• a third via on the second wiring and electrically connected to the second wiring;
• and
• a third wiring on the third via and electrically connected to the third via,
• wherein the first wiring has a first end surface and a second end surface opposing each other,
• wherein the second wiring has a third end surface and a fourth end surface opposing each other,
• wherein the third wiring has a fifth end surface and a sixth end surface opposing each other,
• wherein the first via has a first side adjacent to the first end surface, and a second side opposing the first side,
• wherein the second via has a third side adjacent to the second end surface of the first wiring and a fourth side adjacent to the third end surface of the second wiring,
• wherein the third via has a fifth side adjacent to the fourth end surface of the second wiring and a sixth side adjacent to the fifth end surface of the third wiring, and
• wherein a distance between an upper end of the first side of the first via and a lower end of the first end surface of the first wiring is less than a distance between an upper end of the fourth end surface of the second wiring and a lower end of the fifth side of the third via.

A semiconductor device comprising:

• a lower conductive pattern on a semiconductor substrate;
• an upper wiring on the lower conductive pattern;
• and
• a via between the lower conductive pattern and the upper wiring;
• a lower etch-stop layer;
• a lower insulating layer on the lower etch-stop layer;
• an upper etch-stop layer on the lower insulating layer;
• and
• an upper insulating layer on the upper etch-stop layer,
• wherein the lower conductive pattern has a first end surface and a second end surface opposing each other,
• wherein the upper wiring has a third end surface and a fourth end surface opposing each other,
• wherein the via has a first side adjacent to the second end surface of the lower conductive pattern and a second side adjacent to the third end surface of the upper wiring,
• wherein a distance between a lower end of the first side of the via and an upper end of the second end surface of the lower conductive pattern is less than ⅓ of a width of a top surface of the via, and
• wherein a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via,
• wherein the lower insulating layer and the upper insulating layer include a silicon oxide or a low-k dielectric material,
• wherein the lower etch-stop layer and the upper etch-stop layer include a high-k dielectric material,
• wherein the lower etch-stop layer and the lower insulating layer border a side of the via, and
• wherein the upper etch-stop layer and the upper insulating layer border a side of the upper wiring.