US 11,239,157 B2 · Package structure and package-on-package structure

Abstract

A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

Claims20

Dependent claims

A package structure, comprising:

a semiconductor chip, the semiconductor chip comprises:
a die substrate;
an integrated device disposed on the die substrate, wherein the integrated device includes a substrate layer, a capacitor embedded in the substrate layer, a plurality of through vias located in the substrate layer and surrounding the capacitor;
a plurality of conductive posts disposed on the die substrate and surrounding the integrated device;
and
a protection layer encapsulating the integrated device and the plurality of conductive posts;
a plurality of conductive bumps disposed on the plurality of conductive posts and on the plurality of through vias;
an insulating encapsulant encapsulating the semiconductor chip;
a redistribution layer disposed on the semiconductor chip and over the insulating encapsulant, wherein the semiconductor chip is electrically connected to the redistribution layer through the plurality of conductive bumps;
and
a plurality of conductive balls disposed on the redistribution layer.

8 more elements

A package-on-package structure, comprising:

a package structure, wherein the package structure comprises:
a semiconductor chip, the semiconductor chip comprises:
a die substrate;
a plurality of first bonding structures disposed on the die substrate;
a first passivation layer disposed on the die substrate and encapsulating the plurality of first bonding structures;
a plurality of second bonding structures hybrid bonded to the plurality of first bonding structures;
a second passivation layer disposed on the first passivation layer and encapsulating the plurality of second bonding structures;
a substrate layer disposed on the second passivation layer;
an integrated component located in the substrate layer;
and
a plurality of conductive bumps disposed on the substrate layer and over the first passivation layer and the second passivation layer;
an insulating encapsulant encapsulating the semiconductor chip;
and
a redistribution layer disposed on the insulating encapsulant and electrically connected to the plurality of conductive bumps of the semiconductor chip;
a second package stacked on the package structure, and electrically connected to the package structure through a plurality of conductive balls.

12 more elements

Dependencies are inferred from the claim text.

Package structure and package-on-package structure

Life of this patent

Package structure and package-on-package structure

Life of this patent

Abstract

Claims20