Methods of packaging semiconductor devices and packaged semiconductor devices

A method of packaging a semiconductor device, the method comprising:

• forming an insulating material over a carrier, the insulating material having a planar topmost surface;
• after forming the insulating material, forming on and extending outward from the planar topmost surface of the insulating material a plurality of through-vias, each of the plurality of through-vias comprising a first width;
• coupling a plurality of dies to the insulating material;
• disposing a molding material around the plurality of through-vias, around the plurality of dies, and between the plurality of through-vias and the plurality of dies;
• forming an interconnect structure over the plurality of through-vias, the plurality of dies, and the molding material;
• removing the carrier;
• forming a protective film over the insulating material, after removing the carrier;
• removing a portion of the insulating material proximate each of the plurality of through-vias, wherein the portion of the insulating material proximate each of the plurality of through-vias removed comprises a second width, the second width being less than the first width, wherein removing the portion of the insulating material proximate each of the plurality of through-vias further comprises removing a portion of the protective film proximate each of the plurality of through-vias;
• and
• dicing the insulating material, the molding material, and the interconnect structure to form a plurality of packaged semiconductor devices.

A method of manufacturing a packaged semiconductor device, the method comprising:

• providing an integrated circuit die on an insulating material over a substrate;
• dispensing a molding material disposed around the integrated circuit die, wherein after the dispensing the molding material a plurality of through-vias are disposed within the molding material, each of the plurality of through-vias comprising a constant first width of conductive material as each of the plurality of through-vias extend from a first side of the molding material to a second side of the molding material, the first width measured from a first sidewall of the molding material to a second sidewall of the molding material;
• removing the substrate;
• depositing a protective film adjacent the insulating material after the removing the substrate;
• removing a portion of the insulating material proximate each of the plurality of through-vias to expose a portion of each of the plurality of through vias, each exposed portion having a second width, the second width being less than the first width, wherein the removing the portion of the insulating material further comprises removing a portion of the protective film;
• forming an interconnect structure disposed on a second side of the integrated circuit die, the molding material, and the plurality of through-vias, the interconnect structure having a first end in physical contact with a contact pad on the integrated circuit die and a second end in physical contact with at least one through-via of the plurality of through-vias, the second end being electrically continuous with the first end;
• and
• forming a plurality of connectors coupled to respective ones of the plurality of through-vias through the insulating material, wherein the plurality of connectors each comprises a solder ball and an intermetallic compound.