Semiconductor power device with corresponding package and related manufacturing process

A process, comprising:

• coupling a semiconductor die to a leadframe, wherein a first surface of the semiconductor die comprises a plurality of source regions, a plurality of gate regions, and one or more contact pads coupled to the plurality of gate regions, wherein the semiconductor die comprises a drain at a second surface, wherein the plurality of source regions are rectangular shaped in plan view at the first surface;
• and
• coupling a first multilayer stack to the active surface of the semiconductor die, the first multilayer stack including an upper metal layer, a lower metal layer, and an insulating layer between the upper metal layer and the lower metal layer, wherein the lower metal layer comprises a plurality of contact projections extending toward the semiconductor die and electrically coupled to the plurality of source regions of the semiconductor die, wherein insulation regions are provided between the plurality of contact projections and coupled to the plurality of gate regions.

A semiconductor power device, comprising:

• a semiconductor package having a semiconductor die having an active surface having a plurality of source regions, a plurality of gate regions, and one or more contact pads coupled to the plurality of gate regions, wherein the semiconductor die comprises a drain at a second surface, wherein the plurality of source regions are rectangular shaped with a longitudinal length that extends in direction that is parallel with the first surface of the semiconductor die;
• and
• a multilayer stack arranged over the active surface, the multilayer stack including an upper metal layer, a lower metal layer, and an insulating layer between the upper and lower metal layers, wherein the lower metal layer comprises a plurality of contact projections that extend toward and are electrically coupled to the plurality of source regions of the semiconductor die, wherein insulation regions are provided at the plurality of contact projections and face respective gate regions of the plurality of gate regions.