Semiconductor device having buried gate structure and method for fabricating the same
AssigneeSK hynix Inc.
InventorsDong-Soo Kim, Se-Han Kwon
Life of this patent
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Abstract
A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
Claims19
A method for fabricating a semiconductor device, comprising:
- forming a trench in a substrate;
- forming a gate dielectric layer over a surface of the trench;
- forming a lower gate, which partially fills the trench, over the gate dielectric layer;
- forming a low work function layer, which has a lower work function than the lower gate, over the lower gate by partially filling the trench over the lower gate while leaving an upper part of the gate dielectric layer in the trench exposed;
- forming a spacer over the low work function layer and over the exposed part of the gate dielectric layer;
- etching the low work function layer to be self-aligned with the spacer, in order to form a vertical gate on both upper edges of the lower gate;
- and
- forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
A method for fabricating a semiconductor device, comprising:
- forming a trench in a substrate;
- forming a gate dielectric layer over a surface of the trench;
- forming a lower gate, which partially fills the trench, over the gate dielectric layer;
- forming a low work function layer, which has a lower work function than the lower gate, over the lower gate;
- forming a spacer over the low work function layer;
- etching the low work function layer to be self-aligned with the spacer, in order to form a vertical gate on both upper edges of the lower gate;
- forming an upper gate over the lower gate between inner sidewalls of the vertical gate;
- and
- removing the spacer before the forming of the upper gate on the lower gate between the inner sidewalls of the vertical gate.
A method for fabricating a semiconductor device, comprising:
- forming a trench in a substrate;
- forming a gate dielectric layer over a surface of the trench;
- forming a lower gate, which partially fills the trench, over the gate dielectric layer;
- forming a low work function layer, which has a lower work function than the lower gate, over the lower gate;
- forming a spacer over the low work function layer;
- etching the low work function layer to be self-aligned with the spacer, in order to form a vertical gate on both upper edges of the lower gate;
- forming an upper gate over the lower gate between inner sidewalls of the vertical gate;
- and
- forming a barrier layer on the lower gate before the forming of the low work function layer,
- wherein the forming of the barrier layer on the lower gate comprises exposing a top surface of the lower gate to a plasma treatment, in order to form the barrier layer.
Dependencies are inferred from the claim text.