Replacement gate dielectric in three-node access device formation for vertical three dimensional (3D) memory

A method for forming memory arrays having vertically stacked memory cells and having laterally oriented access devices with vertically oriented access lines, comprising:

• depositing layers of a first dielectric material and a sacrificial material, in repeating iterations vertically to form a vertical stack;
• patterning and etching the vertical stack to form a first vertical opening through the vertically repeating layers;
• depositing a conductive material, via the first vertical opening, onto the surface of a sacrificial gate dielectric material;
• etching the vertical stack to form a second vertical opening to expose sidewalls of the vertical stack extending in a first horizontal direction;
• etching the vertical stack through the first horizontal direction to form a first horizontal opening;
• etching a portion of the sacrificial gate dielectric material through the first horizontal direction leaving another portion of the sacrificial gate dielectric material to maintain a structure of the vertical stack;
• depositing a replacement gate dielectric material with a high dielectric constant (high-k) material;
• and
• forming the first source/drain material on a top surface of the sacrificial material.

A method for forming memory arrays having vertically stacked memory cells and having laterally oriented access devices with vertically oriented access lines, comprising:

• depositing layers of a first dielectric material and a sacrificial semiconductor material, in repeating iterations vertically to form a vertical stack;
• forming a first vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose first sidewalls adjacent a first region of the sacrificial semiconductor material;
• sequentially forming a conductive material, via the first vertical opening, onto the surface of a sacrificial gate dielectric material;
• forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second sidewalls of the vertical stack adjacent a second region of the sacrificial semiconductor material;
• selectively removing the first region to form a first horizontal opening in the sacrificial semiconductor material;
• removing a portion of the sacrificial gate dielectric material through the first horizontal direction;
• using an atomic layer deposition (ALD) process to deposit a replacement gate dielectric material with a high dielectric constant (high-k) material;
• forming a source/drain material, a channel material and a second source/drain material sequentially in the first horizontal opening to form a horizontally oriented three-node access device;
• and
• forming a second horizontal opening in the vertical stack in which to form a storage node electrically coupled to the source/drain material after formation of the three-node access device in the first region.