Semiconductor device with reduced contact resistance and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Chiang Tsai, Jhy-Huei Chen
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Abstract
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.
Claims20
A semiconductor device, comprising:
- a substrate;
- a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode;
- a first metal layer disposed over the gate stack, wherein the first metal layer physically contacts the spacers, the gate dielectric layer and the gate electrode, wherein a top surface of the first metal layer is below a top surface of the spacers;
- and
- a gate via disposed over the first metal layer.
A device comprising:
- a first gate stack disposed over a substrate, the gate stack including a gate dielectric layer and a gate electrode layer;
- a first sidewall spacer disposed along a first sidewall of the first gate stack and a second sidewall spacer disposed along an opposing second sidewall of the first gate stack, the second sidewall being opposite the first sidewall of the of the first gate stack;
- a first metal layer disposed directly on the gate electrode layer and extending from the first sidewall spacer to the second sidewall spacer such that the first metal layer physically contacts the first sidewall spacer and the second sidewall spacer, wherein a top surface of the first metal layer is recessed relative to a top surface of the first sidewall spacer, and wherein the top surfaces of the first metal layer and the first sidewall spacer each face away from the substrate;
- a gate via extending between the first and second sidewall spacers to interface with the first metal layer;
- a source/drain contact disposed over the substrate;
- a second metal layer disposed directly on the source/drain contact;
- and
- a source/drain via extending to the second metal layer.
A device comprising:
- a first gate stack disposed over a substrate, the gate stack including a gate dielectric layer and a gate electrode layer;
- a first sidewall spacer disposed along a first sidewall of the first gate stack and a second sidewall spacer disposed along an opposing second sidewall of the first gate stack, the second sidewall being opposite the first sidewall of the of the first gate stack;
- a first metal layer disposed directly on the gate electrode layer and extending from the first sidewall spacer to the second sidewall spacer such that the first metal layer physically contacts the first sidewall spacer and the second sidewall spacer, and wherein the first sidewall spacer extends to a first height above the substrate and the first metal layer extends to a second height above the substrate, the second height being less than the first height, and
- wherein the gate dielectric layer physically contacts the first and second sidewall spacers and is positioned between the gate electrode layer and the first and second sidewall spacers such that the gate dielectric layer prevents the gate electrode layer from interfacing with the first and second sidewall spacers.
Dependencies are inferred from the claim text.