Passivating silicide-based approaches for conductive via fabrication and structures resulting therefrom

An integrated circuit structure, comprising:

• a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate, wherein each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer;
• a metal silicide layer on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines, wherein the metal silicide layer has an uppermost surface below the uppermost surface of the ILD layer;
• a hardmask layer on the metal silicide layer and on the uppermost surface of the ILD layer, the hardmask layer comprising a first hardmask component on and aligned with the metal silicide layer, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer, the first and second hardmask components differing in composition from one another;
• and
• a conductive via in an opening in the hardmask layer and on a portion of the metal silicide layer portion on one of the plurality of conductive lines, wherein a portion of the conductive via is on a portion of the second hardmask component of the hardmask layer.

An integrated circuit structure, comprising:

• a plurality of alternating first and second conductive lines along a same direction of a back end of line (BEOL) metallization layer in an inter-layer dielectric (ILD) layer above a substrate, wherein each of the plurality of alternating first and second conductive lines is recessed relative to an uppermost surface of the ILD layer;
• a first metal silicide layer on the first conductive lines, in recess regions above each of the first conductive lines;
• a second metal silicide layer on the second conductive lines, in recess regions above each of the second conductive lines, the second metal silicide layer differing in composition from the first metal silicide layer;
• a hardmask layer on the first metal silicide layer, on the second metal silicide layer and on the uppermost surface of the ILD layer, the hardmask layer comprising a first hardmask component on and aligned with the first metal silicide layer, and a second hardmask component on an aligned with the second metal silicide layer, the first and second hardmask components differing in composition from one another;
• and
• a conductive via in an opening in the hardmask layer and on a portion of the second metal silicide layer on one of the second conductive lines, wherein a portion of the conductive via is on a portion of the first hardmask component of the hardmask layer.

A method of fabricating a back end of line (BEOL) metallization layer, the method comprising:

• forming a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate;
• recessing the plurality of conductive lines relative to an uppermost surface of the ILD layer;
• subsequent to the recessing, forming a metal silicide layer on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines, wherein the metal silicide layer has an uppermost surface below the uppermost surface of the ILD layer;
• forming a hardmask layer on the metal silicide layer and on the uppermost surface of the ILD layer, the hardmask layer comprising a first hardmask component on and aligned with the metal silicide layer, and a second hardmask component on regions of the uppermost surface of the ILD layer, the first and second hardmask components differing in composition from one another;
• forming an opening in the hardmask layer by removing a portion of the first hardmask component from over a portion of the metal silicide layer on one of the plurality of conductive lines;
• and
• forming a conductive via in the opening in the hardmask layer and on the portion of the metal silicide layer on the one of the plurality of conductive lines.