Semiconductor memory having reduced interference between bit lines and word lines

A flash memory device, comprising:

• a substrate;
• a plurality of active regions and a plurality of isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction;
• a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, wherein each gate structure of the plurality of gate structures comprises a tunneling dielectric layer on an active region of the plurality of active regions, a floating gate on the tunneling dielectric layer, an intergate dielectric layer on the floating gate, and a control gate on the intergate dielectric layer;
• a gap structure between the gate structures;
• an isolation material having a convex bottom filling an upper portion of the gap structure and a top surface coplanar with a top surface of the plurality of gate structures, and leaving a first air gap in a lower portion of the gap structure;
• and
• a metal layer on the control gate and not on the first air gap,
• wherein the first air gap comprises a bottom surface coplanar with a bottom surface of the tunneling dielectric layer, and
• the metal layer has a bottom surface coplanar with the top surface of the isolation material.