High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

A multilayer structure comprising:

• a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm, and further wherein the single crystal semiconductor handle substrate has a handle crystal orientation;
• an epitaxial layer in direct contact with the front surface of the single crystal semiconductor handle substrate, wherein the epitaxial layer has a resistivity between about 100 Ohm-cm and about 5000 Ohm-cm and further wherein the epitaxial layer has a crystal orientation that is the same as the handle crystal orientation;
• a charge trapping layer in direct contact with the epitaxial layer, the charge trapping layer comprising polycrystalline silicon and having a resistivity of at least about 3000 Ohm-cm;
• a dielectric layer in direct contact with the charge trapping layer;
• and
• a single crystal semiconductor device layer in direct contact with the dielectric layer.