Package-on-package structure

A method comprising:

• forming a plurality of interconnect structures over a carrier, wherein the plurality of interconnect structures comprises a dielectric layer and a redistribution line over the dielectric layer;
• after forming the plurality of interconnect structures, attaching a first semiconductor die and a second semiconductor die on a first side of the plurality of interconnect structures;
• after attaching the first semiconductor die and the second semiconductor die, forming a first underfill layer between the first semiconductor die and the plurality of interconnect structures, and a second underfill layer between the second semiconductor die and the plurality of interconnect structures;
• mounting a first top package over the first semiconductor die and a second top package over the second semiconductor die to form a package-on-package device;
• forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the encapsulation layer directly contacts the first underfill layer;
• mounting a plurality of first bumps on a second side of the plurality of interconnect structures;
• and
• sawing the package-on-package device to form a first chip comprising the first top package and a second chip comprising the second top package.

A method comprising:

• forming a bottom package including a plurality of interconnect structures on a carrier, wherein the plurality of interconnect structures comprises a metal line and a via;
• after forming the bottom package, attaching a first semiconductor die and a second semiconductor die on a first side of the bottom package;
• mounting a first top package and a second top package over the bottom package, wherein each of the first top package and the second top package comprises a first substrate, a die on the first substrate, and a first encapsulant over the first substrate and the die, wherein the first semiconductor die is between two bumps of the first top package and the second semiconductor die is between two bumps of the second top package, wherein mounting the first top package comprises forming a solder connection on a conductive element of the bottom package, the solder connection contacting a top surface and opposing sidewalls of the conductive element;
• forming an encapsulation layer over the first top package and the second top package, wherein the encapsulation layer extends completely over the first top package and the second top package, wherein the encapsulation layer completely separates the first top package from the second top package, and wherein the encapsulation layer extends between the bottom package and the first top package and between the bottom package and the second top package;
• and
• after forming the encapsulation layer, detaching the carrier from the plurality of interconnect structures.