Cut metal gate process for reducing transistor spacing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
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Abstract
A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other.
Claims20
A semiconductor structure, comprising:
- a substrate;
- a pair of first fins extending from the substrate;
- a pair of second fins extending from the substrate;
- an isolation feature over the substrate and separating bottom portions of the first and the second fins;
- a pair of first epitaxial semiconductor features over the pair of first fins, respectively;
- a pair of second epitaxial semiconductor features over the pair of second fins, respectively;
- a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features, wherein the pair of second epitaxial semiconductor features merge with each other;
- and
- two contact features on the pair of first epitaxial semiconductor features respectively, wherein each of the two contact features is in direct contact with a side surface of the first dielectric feature and a side surface of another dielectric feature that includes a different material than the first dielectric feature.
A semiconductor structure, comprising:
- a substrate;
- an isolation structure over the substrate;
- fins oriented lengthwise along a first direction, the fins extending from the substrate and through the isolation structure;
- gate structures over the isolation structure and the fins and oriented lengthwise along a second direction generally perpendicular to the first direction;
- a first dielectric feature disposed above the isolation structure and lengthwise between two of the fins, the first dielectric feature extending from an edge of a first one of the gate structures to an edge of a second one of the gate structures;
- and
- a second dielectric feature disposed above the isolation structure and separating the second one of the gate structures into two portions, wherein the first dielectric feature is wider than the second dielectric feature along the second direction.
A semiconductor structure, comprising:
- a substrate;
- first and second fins extending from the substrate;
- an isolation feature over the substrate and between bottom portions of the first and the second fins;
- first and second epitaxial semiconductor features over the first and the second fins, respectively;
- a first dielectric feature between the first and the second epitaxial semiconductor features, wherein a first portion of the first dielectric feature contacts the first and the second epitaxial semiconductor features, and a second portion of the first dielectric feature extends below the first portion and does not contact the first and the second epitaxial semiconductor features;
- and
- a contact etch stop layer (CESL) on a surface of the first epitaxial semiconductor feature, wherein the CESL is free from another surface of the first epitaxial semiconductor feature that is between the first epitaxial semiconductor feature and the second portion of the first dielectric feature.
Dependencies are inferred from the claim text.