Memory system, memory controller, and method of operating memory system
AssigneeSK hynix Inc.
InventorsMyung Jin Jo, Dae Sung Kim
Life of this patent
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Abstract
A memory system performs Error Correcting Code (ECC) decoding on data read from a plurality of target memory cells of a memory device, determines whether to update a read bias used in read operations of the memory device according to results of the ECC decoding, and then may update a value of the read bias based on result data produced by the ECC decoding and the number of data bits corrected by the ECC decoding, thereby optimizing the read bias value according to a change in a threshold voltage distribution of the memory cell, and increasing the likelihood of success of the ECC decoding.
Claims16
A memory system comprising:
- a memory device;
- and
- a memory controller configured to control the memory device, wherein the memory controller:
- performs Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in the memory device, and
- in response to the ECC decoding succeeding:
- determines whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and
- in response to determining to update the one or more read biases, updates a read bias of the one or more read biases based on information regarding:
- i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding, and
- wherein the memory controller determines a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate when updating the read bias.
A memory controller comprising:
- a memory interface configured to communicate with a memory device;
- and
- a control circuit configured to control the memory device, wherein the control circuit:
- performs Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in the memory device, and
- in response to the ECC decoding succeeding:
- determines whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and
- in response to determining to update the one or more read biases, updates a read bias of the one or more read biases based on information regarding:
- i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding, and
- wherein the control circuit determines a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate, when updating the read bias.
A method of operating a memory system, the method comprising:
- successfully performing Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in a memory device;
- and
- in response to the ECC decoding succeeding:
- determining whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and
- in response to determining to update the one or more read biases, updating a read bias of the one or more read biases based on information regarding:
- i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding,
- wherein updating of the read bias comprises determining a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate, when updating the read bias.
Dependencies are inferred from the claim text.