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US 11,238,949 B2Granted
Memory devices configured to test data path integrity
AssigneeMicron Technology, Inc.
InventorTerry Grunzke
Life of this patent
Estimating the term…
Abstract
Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.
Claims20
A memory device, comprising:
- an array of memory cells;
- a first register in communication with the array of memory cells;
- a second register in communication with the first register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the first register;
- load the first set of data into a first portion of the second register;
- receive a set of test data from an external device;
- write the set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register;
- read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register;
- and
- output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register.
10 more elements
A memory device, comprising:
- an array of memory cells;
- a first register in communication with the array of memory cells;
- a second resister in communication with the first register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the first register;
- load the first set of data into a first portion of the second register;
- write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register;
- read the set of test data from the second portion of the second register during the reading of the second set of from the array of memory cells to the first register;
- and
- output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register;
- and
- wherein the controller is further configured to accept commands to cause the memory device to:
- enter a debug mode of the memory device prior to loading the first set of data into the first portion of the second register;
- and
- exit the debug mode after outputting the set of test data read from the second portion of the second register.
14 more elements
A memory device, comprising:
- an array of memory cells;
- a first register in communication with the array of memory cells;
- a second register in communication with the first register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the first register;
- load the first set of data into a first portion of the second register;
- write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register;
- read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register;
- and
- output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register;
- wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the second register comprises the controller being configured to cause the memory device to read data from the first portion of the second register and from the second portion of the second register.
10 more elements
A memory device, comprising:
- an array of memory cells;
- a first register in communication with the array of memory cells;
- a second register in communication with the first register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the first register;
- load the first set of data into a first portion of the second register;
- write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register;
- read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register;
- and
- output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register;
- wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the second register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the second register without reading data from the first portion of the second register.
10 more elements
A memory device, comprising:
- an array of memory cells;
- a first register in communication with the array of memory cells;
- a second register in communication with the first register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the first register;
- load the first set of data into a first portion of the second register;
- clear the second register after loading the first set of data into the second register and during a reading of a second set of data from the array of memory cells to the first register, then write a set of test data to a second portion of the cleared second register during the reading of the second set of data from the array of memory cells to the first register;
- read the set of test data from the second portion of the cleared second register during the reading of the second set of data from the array of memory cells to the first register;
- and
- outputting the set of test data, read from the second portion of the cleared second register, from the memory device.
9 more elements
A memory device, comprising:
- an array of memory cells;
- a page register in communication with the array of memory cells;
- a cache register in communication with the page register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the page register;
- load the first set of data into a first portion of the cache register;
- receive a set of test data from an external device;
- write the set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register;
- read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register;
- and
- output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register.
10 more elements
A memory device, comprising:
- an array of memory cells;
- a page register in communication with the array of memory cells;
- a cache register in communication with the page register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the page register;
- load the first set of data into a first portion of the cache register;
- write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register;
- read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register;
- and
- output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register;
- and
- wherein the controller is further configured to accept commands to cause the memory device to:
- enter a debug mode of the memory device prior to loading the first set of data into the first portion of the cache register;
- and
- exit the debug mode after outputting the set of test data read from the second portion of the cache register.
14 more elements
A memory device, comprising:
- an array of memory cells;
- a page register in communication with the array of memory cells;
- a cache register in communication with the page register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the page register;
- load the first set of data into a first portion of the cache register;
- write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register;
- read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register;
- and
- output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register;
- wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register and to read the first set of data from the first portion of the cache register.
10 more elements
A memory device, comprising:
- an array of memory cells;
- a page register in communication with the array of memory cells;
- a cache register in communication with the page register;
- and
- a controller for access of the array of memory cells;
- wherein the controller is configured to accept a sequence of commands to cause the memory device to:
- read a first set of data from the array of memory cells into the page register;
- load the first set of data into a first portion of the cache register;
- write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register;
- read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register;
- and
- output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register;
- wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register without reading data from the first portion of the cache register.
10 more elements
Dependencies are inferred from the claim text.