Apparatus and methods for seeding operations concurrently with data line set operations

A memory, comprising:

• an array of memory cells comprising a first string of memory cells selectively connected to a first data line and a second string of memory cells selectively connected to a second data line, wherein each memory cell of the first string of memory cells is connected to a respective access line of a plurality of access lines;
• and
• a controller to access the array of memory cells, the controller configured to:
• perform a sense operation on a particular memory cell of the first string of memory cells;
• apply a first voltage level to the respective access line of the plurality of access lines for a second memory cell of the first string of memory cells;
• apply a second voltage level higher than the first voltage level to the respective access line of the plurality of access lines for the particular memory cell;
• apply a third voltage level to the first data line;
• and
• apply a fourth voltage level higher than the third voltage level to the second data line.

A memory, comprising:

• a common source;
• a first data line and a second data line;
• an array of memory cells comprising a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source;
• a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells;
• and
• a controller to access the array of memory cells, the controller configured to:
• perform a sense operation on a particular memory cell of the first string of memory cells;
• apply a first voltage level to respective access lines of the plurality of access lines for a first subset of memory cells of the first string of memory cells, wherein each memory cell of the first subset of memory cells is between the particular memory cell and the first data line;
• apply the first voltage level to respective access lines of the plurality of access lines for a second subset of memory cells of the first string of memory cells, wherein each memory cell of the second subset of memory cells is between the particular memory cell and the first subset of memory cells;
• and
• apply a second voltage level higher than the first voltage level to the respective access line of the plurality of access lines for the particular memory cell.