Method for writing an electrically erasable and programmable non volatile memory and corresponding integrated circuit

A method for writing to an electrically erasable and programmable non-volatile memory, the method comprising:

• operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, and wherein operatively connecting the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, the enabled state comprising enabling access to functions of the filter circuit, the disabled state comprising disabling access to functions of the filter circuit;
• generating, by the oscillator circuit, an oscillation signal;
• regulating the oscillation signal by dynamically adjusting a frequency of the oscillation signal relative to a time constant of the filter circuit to generate a clock signal for timing a write cycle, wherein the generating the clock signal comprises dividing a frequency of the regulated oscillation signal;
• and
• generating write high voltages in the write cycle by switching capacitive elements to supply voltages, wherein switching the capacitive elements is timed by the oscillation signal.

An integrated circuit comprising:

• a state machine configured to control write operations in a write cycle timed by a clock signal;
• a communication interface comprising a filter circuit and configured to be physically connected to a bus;
• and
• a clock signal generator comprising an oscillator circuit and logic gates connected to an input of the filter circuit and to an output of the filter circuit, the logic gates configured to generate signals with a constant arbitrary value in presence of a mode selection signal in order to operatively disconnect the filter circuit and the communication interface, the clock signal generator configured to:
• operatively disconnect the filter circuit from the communication interface;
• operatively connect the filter circuit to the oscillator circuit after operatively disconnecting the filter circuit from the communication interface, wherein operatively connect the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, the enabled state comprising enabling access to functions of the filter circuit, the disabled state comprising disabling access to functions of the filter circuit;
• generate an oscillation signal;
• and
• regulate the oscillation signal by the filter circuit to generate the clock signal in the write cycle, wherein the integrated circuit is an integrated circuit of an electrically erasable and programmable non-volatile memory.