Semiconductor memory device

A memory system comprising:

• a semiconductor memory device including a first memory cell, a second memory cell, a first word line, a second word line and a first bit line, the first memory cell being capable of holding data, the second memory cell being capable of holding data, the first word line being coupled to the first memory cell, the second word line being coupled to the second memory cell, the first bit line being capable of being electrically coupled to both the first memory cell and the second memory cell, the first memory cell sharing a semiconductor layer with the second memory cell;
• and
• a controller configured to control the semiconductor memory device, wherein
• the controller is configured to send a first write command specifying the first memory cell,
• in response to the first write command, the semiconductor memory device is configured to execute a first operation, a second operation after executing the first operation, and a third operation after executing the second operation,
• the first operation includes applying a first voltage to a word line corresponding to a non-selected memory cell,
• the second operation includes applying a second voltage higher than the first voltage to the word line corresponding to the non-selected memory cell,
• the third operation includes applying a third voltage higher than the second voltage to the word line corresponding to the non-selected memory cell and applying a fourth voltage lower than both the third voltage and the second voltage to a word line corresponding to a selected memory cell,
• the controller is configured to send a second write command specifying the second memory cell, and
• in response to the second write command, the semiconductor memory device is configured to execute the third operation without executing the first and second operations executed during a period between the semiconductor memory device entering to a busy state and returning to a ready state.